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1 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rev. 0.9 / dec.2000 overview the rambus direct rdram? is a general purpose high- performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. the 256/288-mbit direct rambus drams (rdram ) are extremely high-speed cmos drams organized as 16m words by 16 or 18 bits. the use of rambus signaling level (rsl) technology permits 600mhz to 800mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). the architecture of the direct rdrams allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdram's 32 banks support up to four simultaneous transactions. system oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. the two data bits in the x18 organiza- tion are general and can be used for additional storage and bandwidth or for error correction. features 0 highest sustained bandwidth per dram device - 1.6gb/s sustained data transfer rate - separate control and data buses for maximized efficiency - separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simul- taneously at full bandwidth data rates 0 low latency features - write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - interleaved transactions 0 advanced power management: - multiple low power states allows flexibility in power consumption versus time to transition to active state - power-down self-refresh 0 organization: 2kbyte pages and 32 banks, x 16/18 - x18 organization allows ecc configurations or increased storage/bandwidth - x16 organization for low cost applications 0 uses rambus signaling level (rsl) for up to 800mhz operation the 256 / 288 -mbit direct rdrams are offered in a ubga package suitable for desktop as well as low-profile add-in card and mobile applications. direct rdrams operate from a 2.5 volt supply. key timing parameters / part numbers figure 1: direct rdram ubga p ackage organization a a. the bank ?32s? designation indicates that this rdram core is composed of 32 banks which use a ?split? bank architecture. i/o freq. mhz core access time (ns) part number 512 kx16x32s 600 53 hy5r 256 hc653 512 kx16x32s 711 45 hy5r 256 hc745 512 kx16x32s 800 45 hy5r 256 hc845 512 kx16x32s 800 4 0 hy5r 256 hc840 512 kx1 8x 32s 600 53 hy5r 288 hc653 512 kx1 8x 32s 711 45 hy5r 288 hc745 512 kx1 8x 32s 800 45 hy5r 288 hc845 512 kx1 8x 32s 800 4 0 hy5r 288 hc840 this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described. no patent licenses are implied.
2 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary pinouts and definitions center-bonded devices these tables shows the pin assignments of the center-bonded rdram package from the top-side of the package (the view looking down on the package as it is mounted on the circuit board). the mechanical dimensions of this package are shown in a later section. refer to section " " on page 60. ( note : pin#1 is at the a1 position. ) table 1: center-bonded device (top view) 10 vdd gnd vdd gnd vdd vdd vdd vdd gnd vdd 9 8 gnd vdd cmd vdd gnd gnda gnda vdd vdd gnd gnd vdd vdd gnd gnd vcmos vdd gnd 7 vdd dqa8 dqa7 dqa5 dqa3 dqa1 ctm ctm row 2 row 0 col3 col1 dqb1 dqb3 dqb5 dqb7 dqb8 vdd 6 5 4 gnd gnd dqa6 dqa4 dqa2 dqa0 cfm cfm row 1 col4 col2 col0 dqb0 dqb2 dqb4 dqb6 gnd gnd 3 vdd gnd sck vcmos gnd vdd gnd vdda vref gnd vdd gnd gnd vdd sio0 sio1 gnd vdd 2 1 vdd gnd gnd vdd gnd gnd gnd gnd gnd vdd a b c d e f g h j k l m n p r s t u
rev.0.9 / dec.2000 3 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary table 2: pin description signal i/o type # pins center description sio1,sio0 i/o cmos a 2 serial input/output. pins for reading from and writing to the control registers using a serial access protocol. also used for power manage- ment. cmd i cmos a 1 command input. pins used in conjunction with sio0 and sio1 for reading from and writing to the control registers. also used for power management . sck i cmos a 1 serial clock input. clock source used for reading from and writing to the control registers v dd 24 supply voltage for the rdram core and interface logic. v dda 1 supply voltage for the rdram analog circuitry. v cmos 2 supply voltage for cmos input/output pins . gnd 28 ground reference for rdram core and interface. gnda 2 ground reference for rdram analog circuitry. dqa8..dqa0 i/o rsl b 9 data byte a. nine pins which carry a byte of read or write data between the channel and the rdram. dqa8 is not used by rdrams with a x16 organization. cfm i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. cfmn i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. negative polarity v ref 1 logic threshold reference voltage for rsl signals ctmn i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ctm i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. rq7..rq5 or row2..row0 i rsl b 3 row access control. three pins containing control and address infor- mation for row accesses. rq4..rq0 or col4..col0 i rsl b 5 column access control. five pins containing control and address information for column accesses. dqb8.. dqb0 i/o rsl b 9 data byte b. nine pins which carry a byte of read or write data between the channel and the rdram. dqb8 is not used by rdrams with a x16 organization. total pin count per package 92 a. all cmos signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. all rsl signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
4 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 2: 256 / 288 mbit direct rdram block diagram ban k 31 dqa8 .. dqa0 1 : 8 d e m u x 8 : 1 m u x w r i t e b u f f e r 1 : 8 d e m u x w r i t e b u f f e r 8 : 1 m u x ban k 30 ban k 29 bank 1 8 bank 1 7 ban k 16 ban k 15 ban k 14 ban k 13 bank 1 bank 0 s a m p 1 / 2 dqb8 . . d qb0 9 1:8 demux 1:8 demux packet decode 9 5 3 row 2 .. row0 col 4 . . col0 ctm ctmn cfm cfmn 2 sck,cmd rcl k tclk control registers d c cop c bc m a m b d x xop bx d r r rop b r 8 8 7 5 5 5 5 5 6 9 5 5 11 av m s write buffer match match mux match devid 512x128x144 internal dqb data path column decode & mask 72 9 9 72 9 dm refr row decode mux act rd, wr power modes dram core mux xop decode pre x pre c 9 9 9 9 72 9 9 9 pr e r colx colc colm 2 s io0,sio1 sense amp internal dqa data path packet decode row a rowr rc lk rc lk r c l k t c l k r c l k t c l k rq7 . . rq5 or rq4..rq0 or s a m p 0 / 1 s a m p 0 s a m p 1 4 / 1 5 s a m p 1 5 s a m p 1 3 / 1 4 s a m p 1 6 / 1 7 s a m p 1 7 / 1 8 s a m p 1 6 s a m p 2 9 / 3 0 s a m p 3 0 / 3 1 s a m p 3 1 64 x 72 s a m p 1 / 2 72 s a m p 0 / 1 s a m p 0 s a m p 1 4 / 1 5 s a m p 1 5 s a m p 1 3 / 1 4 s a m p 1 6 / 1 7 s a m p 1 7 / 1 8 s a m p 1 6 s a m p 2 9 / 3 0 s a m p 3 0 / 3 1 s a m p 3 1 64 x 72 64x 72 bank 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
5 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rev. 0.9 / dec.2000 general description figure 2: is a block diagram of the 256/288 mbit direct rdram. it consists of two major blocks: a ?core? block built from banks and sense amps similar to those found in other types of dram, and a direct rambus interface block which permits an external controller to access this core at up to 1.6gb/s. control registers: the cmd, sck, sio0, and sio1 pins appear in the upper center of figure 2:. they are used to write and read a block of control registers. these registers supply the rdram configuration information to a controller and they select the operating modes of the device. the refr value is used for tracking the last refreshed row. most importantly, the five bit devid specifies the device address of the rdram on the channel. clocking: the ctm and ctmn pins (clock-to-master) generate tclk (transmit clock), the internal clock used to transmit read data. the cfm and cfmn pins (clock-from- master) generate rclk (receive clock), the internal clock signal used to receive write data and to receive the row and col pins. dqa,dqb pins: these 18 pins carry read (q) and write (d) data across the channel. they are multiplexed/de-multi- plexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the rdram. banks: the 32mbyte core of the rdram is divided into 32 x 1mbyte banks, each organized as 512 rows, with each row containing 128 dualocts(2k bytes), and each dualoct containing 16 bytes. a dualoct is the smallest unit of data that can be addressed. sense amps: the rdram contains 34 sense amps. each sense amp consists of 1k bytes of fast storage (512 bytes for dqa and 512 bytes for dqb) and can hold one- half of one row of one bank of the rdram. the sense amp may hold any of the 1024 half-rows of an associated bank. however, each sense amp is shared between two adjacent banks of the rdram (except for sense amps 0, 15, 16, and 31). this introduces the restriction that adjacent banks may not be simultaneously accessed. rq pins: these pins carry control and address informa- tion. they are broken into two groups. rq7..rq5 are also called row2..row0, and are used primarily for controlling row accesses. rq4..rq0 are also called col4..col0, and are used primarily for controlling column accesses. row pins: the principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the rdram. these pins are de-multiplexed into a 24-bit rowa (row-activate) or rowr (row-operation) packet. col pins: the principle use of these five pins is to manage the transfer of data between the dqa/dqb pins and the sense amps of the rdram. these pins are de-multi- plexed into a 23-bit colc (column-operation) packet and either a 17-bit colm (mask) packet or a 17-bit colx (extended-operation) packet. act command: an act (activate) command from an rowa packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 bytes sense amps for dqa and two for dqb). prer command: a prer (precharge) command from an rowr packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be acti- vated. rd command: the rd (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the dqa/dqb pins of the channel. wr command: the wr (write) command causes a dualoct received from the dqa/dqb data pins of the channel to be loaded into the write buffer. there is also space in the write buffer for the bc bank address and c column address information. the data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subse- quent cop command. a retire can take place during a rd, wr, or nocop to another device, or during a wr or nocop to the same device. the write buffer will not retire during a rd to the same device. the write buffer reduces the delay needed for the internal dqa/dqb data path turn- around. prec precharge: the prec, rda and wra commands are similar to nocop, rd and wr, except that a precharge operation is performed at the end of the column operation. these commands provide a second mechanism for performing precharge. prex precharge: after a rd command, or after a wr command with no byte masking (m=0), a colx packet may be used to specify an extended operation (xop). the most important xop command is prex. this command provides a third mechanism for performing precharge.
6 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary packet format figure 3: shows the formats of the rowa and rowr packets on the row pins. table3 describes the fields which comprise these packets. dr4t and dr4f bits are encoded to contain both the dr4 device address bit and a framing bit which allows the rowa or rowr packet to be recognized by the rdram. the av (rowa/rowr packet selection) bit distinguishes between the two packet types. both the rowa and rowr packet provide a five bit device address and a five bit bank address. an rowa packet uses the remaining bits to specify a nine bit row address, and the rowr packet uses the remaining bits for an eleven bit opcode field. note the use of the ?rsvx? notation to reserve bits for future address field extension. figure 3: also shows the formats of the colc, colm, and colx packets on the col pins. table4 describes the fields which comprise these packets. the colc packet uses the s (start) bit for framing. a colm or colx packet is aligned with this colc packet, and is also framed by the s bit. the 23 bit colc packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. the colc packet specifies a read or write command, as well as some power management commands. the remaining 17 bits are interpreted as a colm (m=1) or colx (m=0) packet. a colm packet is used for a colc write command which needs bytemask control. the colm packet is associated with the colc packet from at least t rtr earlier. an colx packet may be used to specify an independent precharge command. it contains a five bit device address, a five bit bank address, and a five bit opcode. the colx packet may also be used to specify some house- keeping and power management commands. the colx packet is framed within a colc packet but is not otherwise associated with any other packet. table 3: field description for rowa packet and rowr packet field description dr4t,dr4f bits for framing (recognizing) a rowa or rowr packet. also encodes highest device address bit. dr3..dr0 device address for rowa or rowr packet. br4..br0 bank address for rowa or rowr packet. rsvb denotes bits ignored by the rdram. av selects between rowa packet (av=1) and rowr packet (av=0). r8..r0 row address for rowa packet. rsvr denotes bits ignored by the rdram. rop10..rop0 opcode field for rowr packet. specifies precharge, refresh, and power management functions. table 4: field description for colc p acket, colm p acket, and colx p acket field description s bit for framing (recognizing) a colc p acket, and indirectly for framing colm a nd colx p ackets. dc4..dc0 device address for colc p acket. bc 4. .bc0 bank address for colc packet. rsvb denotes bits reserved for future extension.(controller drives 0?s) c6..c0 column address for colc packet. rsvc denotes bits ignored by the rdram. cop3..cop0 opcode field for colc p acket. specifies read, write, precharge, and power management functions. m selects between colm packet (m=1) and colx packet (m=0). ma7..ma0 bytemask write control bits. 1=write, 0=no-write. ma0 controls the earliest byte on dqa8..0. mb7..mb0 bytemask write control bits. 1=write, 0=no-write. mb0 controls the earliest byte on dqb8..0. dx4..dx0 device address for colx packet. bx 4. .bx0 bank address for colx packet. rsvb denotes bits reserved for future extension.(controller drives 0?s) xop4..xop0 opcode field for colx packet. specifies precharge, i ol control, and power management functions.
rev.0.9 / dec.2000 7 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 3: packet formats ctm/cfm col4 col3 col2 col1 col0 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 0 t 1 t 2 t 3 s=1 a m a7 ma5 ma3 ma1 m=1 ma6 ma4 ma2 ma0 m b7 mb4 mb1 m b6 mb3 mb0 mb5 mb2 r2 ctm/cfm row2 dr4t dr2 br0 br3 rsvr r8 r5 row1 dr4f dr1 br1 br4 rsvr r7 r4 r1 row0 dr3 dr0 br2 rsvb av=1 r6 r3 r0 act a0 pre x d0 msk (b1) pre r c 0 wr b1 c4 ctm/cfm col4 dc4 s=1 c6 col3 dc3 c5 c3 col2 dc2 cop1 rsvb bc2 c2 dc1 cop0 bc4 bc1 c1 dc0 cop2 cop3 bc3 bc0 c0 col1 col0 ctm/cfm row2 row1 row0 ctm/cfm col4 col3 col2 col1 col0 rop2 dr4t dr2 br0 br3 rop10 rop8 rop5 dr4f dr1 br1 br4 rop9 rop7 rop4 rop1 dr3 dr0 br2 rsvb av=0 rop6 rop3 rop0 s=1 b dx4 xop4 rsvb bx1 m=0 dx3 xop3 bx4 bx0 dx2 xop2 bx3 dx1 xop1 bx2 dx0 xop0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 rowa p acket colm p acket colc p acket colx p acket rowr p acket ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t packet a the colm is associated with a previous colc, and is aligned with the present colc, indicated by the start bit (s=1) position. b the colx is aligned with the present colc, indicated by the start bit (s=1) position.
8 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary field encoding summary table5 shows how the six device address bits are decoded for the rowa and rowr packets. the dr4t and dr4f encoding merges a fifth device bit with a framing bit. when neither bit is asserted, the device is not selected. note that a broadcast operation is indicated when both bits are set. broadcast operation would typically be used for refresh and power management commands. if the device is selected, the dm (devicematch) signal is asserted and an act or rop command is performed. table6 shows the encodings of the remaining fields of the rowa and rowr packets. an rowa packet is specified by asserting the av bit. this causes the specified row of the specified bank of this device to be loaded into the associated sense amps. an rowr packet is specified when av is not asserted. an 11 bit opcode field encodes a command for one of the banks of this device. the prer command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. the refa (refresh-acti- vate) command is similar to the act command, except the row address comes from an internal register refr, and refr is incremented at the largest bank address. the refp (refresh-precharge) command is identical to a prer command. the napr, naprc, pdnr, attn, and rlxr commands are used for managing the power dissipation of the rdram and are described in more detail in ? power state manage- ment ? on page38. the tcen and tcal commands are used to adjust the output driver slew rate and they are described in more detail in ? current and temperature control ? on page44. table 5: device field encodings for rowa p acket and rowr p acket dr4t dr4f device selection device match signal (dm ) 1 1 all devices (broadcast) dm is set to 1 0 1 one device selected dm is set to 1 if {devid4..devid0} == {0,dr3..dr0} else dm is set to 0 1 0 one device selected dm is set to 1 if {devid4..devid0} == {1,dr3..dr0} else dm is set to 0 0 0 no packet present dm is set to 0 table 6: rowa p acket and rowr p acket field encodings dm a a v rop10..rop0 field n ame command description 10 9 8 7 6 5 4 3 2 :0 0 - - - - - - - - - --- - no operation. 1 1 row address act activate row r8..r0 of bank br4..br0 of device and move device to attn b . 1 0 1 1 0 0 0 x c x x 000 prer precharge bank br4..br0 of this device. 1 0 0 0 0 1 1 0 0 x 000 refa refresh (activate) row refr8..refr0 of bank br 4. .br0 of d evice. increment refr if br 4. .br0 = 1111 (see figure 50:). 1 0 1 0 1 0 1 0 0 x 000 refp precharge bank br 4. .br0 of this devic e after refa (see figure 50:). 1 0 x x 0 0 0 0 1 x 000 pdnr move this device into the powerdown (pdn) power state (see figure 47:). 1 0 x x 0 0 0 1 0 x 000 napr move this device into the nap (nap) power state (see figure 47:). 1 0 x x 0 0 0 1 1 x 000 naprc move this device into the nap (nap) power state conditionally 1 0 x x x x x x x 0 000 attn b move this device into the attention (attn) power state (see figure 45:). 1 0 x x x x x x x 1 000 rlxr move t his device into the standby (stby) power state (see figure 46:). 1 0 0 0 0 0 0 0 0 x 001 tcal temperature calibrate this device (see figure 54:). 1 0 0 0 0 0 0 0 0 x 010 tcen temperature calibrate/enable this device (see figure 54:). 1 0 0 0 0 0 0 0 0 0 000 norop no operation. a. the dm (device match signal) value is determined by the dr4t,dr4f, dr3..dr0 field of the rowa and rowr packets. see table5. b. the attn commend does not cause a rlx-to-attn transition for a broadcast operation.(dr4t/dr4f = 1/1) c. an ?x? entry indicates which commands may be combined. for instance, the three commands prer/naprc/rlxr may be specified in o ne rop value (011000111000).
rev.0.9 / dec.2000 9 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary table7 shows the cop field encoding. the device must be in the attn power state in order to receive colc packets. the colc packet is used primarily to specify rd (read) and wr (write) commands. retire operations (moving data from the write buffer to a sense amp) happen automatically. see figure 17: for a more detailed description. the colc packet can also specify a prec command, which precharges a bank and its associated sense amps. the rda/wra commands are equivalent to combining rd/wr with a prec. rlxc (relax) performs a power mode transi- tion. see ? power state management ? on page38. table8 shows the colm and colx field encodings. the m bit is asserted to specify a colm packet with two 8 bit bytemask fields ma and mb. if the m bit is not asserted, an colx is specified. it has device and bank address fields, and an opcode field. the primary use of the colx packet is to permit an independent prex (precharge) command to be specified without consuming control bandwidth on the row pins. it is also used for the cal(calibrate) and sam (sample) current control commands (see ? current and temperature control ? on page44), and for the rlxx power mode command (see ? power state management ? on page38). table 7: colc p acket field encodings s dc4.. dc0 (select d evice) a cop 3..0 n ame command descriptio n 0 ---- ----- - no operation. 1 / = (devid4 ..0) ----- - retire write buffer of this device. 1 == (devid4 .. 0) x 000 b nocop retire write buffer of this device. 1 == (devid4 .. 0) x 001 wr retire write buffer of this device, then write column c6..c0 of bank bc4..bc0 to write buffer. 1 == (devid4 .. 0) x 010 rsrv reserved, no operation. 1 == (devid4 .. 0) x 011 rd read column c6..c0 of bank bc4..bc0 of this device. 1 == (devid4 .. 0) x 100 prec retire write buffer of this device, then precharge bank bc4..bc0 (see figure 14:). 1 == (devid4 .. 0) x 101 wra same as wr, but precharge bank bc 4. .bc0 after w rite buffer (with new data) i s retired. 1 == (devid4 .. 0) x 110 rsrv reserved, no operation. 1 == (devid4 .. 0) x 111 rda same as rd, but precharge bank bc 4. .bc0 afterward. 1 == (devid4 .. 0) 1 xxx rlxc move this device into the standby (stby) power state (see figure 46:). a. ?/=? means not equal, ?==? means equal. b. an ?x? entry indicates which commands may be combined. for instance, the two commands wr/rlxc may be specified in one cop val ue (1001). table 8: colm p acket and colx p acket field encodings m dx4 .. dx0 (select s d evice ) xop4..0 name command description 1 ---- - msk mb/ma bytemasks used by wr/wra. 0 / = (devid4 ..0) - - no operation. 0 == (devid4 .. 0) 0 0000 noxop no operation. 0 == (devid4 .. 0) 1xx x 0 a prex precharge bank bx4..bx0 of this device (see figure 14:). 0 == (devid4 .. 0) x10x0 cal calibrate (drive) i ol current for this device (see figure 52:). 0 == (devid4 .. 0) x11x0 cal/sam sample ( update) i ol current for this device (see figure 52:). 0 == (devid4 .. 0) xxx10 rlxx move this device into the standby (stby) power state (see figure 46:). 0 == (devid4 .. 0) xxxx1 rsrv reserved, no operation. a. an ?x? entry indicates which commands may be combined. for instance, the two commands prex/rlxx may be specified in one xop v alue (10010).
10 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary dq packet timing figure 4: shows the timing relationship of colc packets with d and q data packets. this document uses a specific convention for measuring time intervals between packets: all packets on the row and col pins (rowa, rowr, colc, colm, colx) use the trailing edge of the packet as a reference point, and all packets on the dqa/dqb pins (d and q) use the leading edge of the packet as a reference point. an rd or rda command will transmit a dualoct of read data q a time t cac later. this time includes one to five cycles of round-trip propagation delay on the channel. the t cac parameter may be programmed to a one of a range of values ( 7, 8, 9, 10, 11, or 12 t cycle ). the value chosen depends upon the number of rdram devices on the channel and the rdram timing bin. see figure 39: for more information. a wr or wra command will receive a dualoct of write data d a time t cwd later. this time does not need to include the round-trip propagation time of the channel since the colc and d packets are traveling in the same direction. when a q packet follows a d packet (shown in the left half of the figure), a gap (t cac -t cwd ) will automatically appear between them because the t cwd value is always less than the t cac value. there will be no gap between the two colc packets with the wr and rd commands which schedule the d and q packets. when a d packet follows a q packet (shown in the right half of the figure), no gap is needed between them because the t cwd value is less than the t cac value. however, , a gap of t cac -t cwd or greater must be inserted between the colc packets with the rd wr commands by the controller so the q and d packets do not overlap. colm packet to d packet mapping figure 5: shows a write operation initiated by a wr command in a colc packet. if a subset of the 16 bytes of write data are to be written, then a colm packet is trans- mitted on the col pins a time t rtr after the colc packet containing the wr command. the m bit of the colm packet is set to indicate that it contains the ma and mb mask fields. note that this colm packet is aligned with the colc packet which causes the write buffer to be retired. see figure 17: for more details. if all 16 bytes of the d data packet are to be written, then no further control information is required. the packet slot that would have been used by the colm packet (t rtr after the colc packet) is available to be used as an colx packet. this could be used for a prex precharge command or for a housekeeping command (this case is not shown). the m bit is not asserted in an colx packet and causes all 16 bytes of the previous wr to be written unconditionally. note that a rd command will never need a colm packet, and will always be able to use the colx packet option (a read opera- tion has no need for the byte-write-enable control bits). figure 5: also shows the mapping between the ma and mb fields of the colm packet and bytes of the d packet on the dqa and dqb pins. each mask bit controls whether a byte of data is written (=1) or not written (=0). figure 4: read (q) and write (d) data packet - timing for t cac = 7, 8, 9, 10, 11, o r 12 t cycle ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 d (d1) rd b1 q (a1) q (a1) wr a1 d (a1) t cwd rd c1 q (a1) q (a1) t cac - t cwd this gap on the dqa/dqb pins a ppears automatically this gap on the col pins m ust be inserted by the controller t cac t cac wr d1 wr d1 d (d1) d (d1) t cac - t cwd t cwd wr d1 q (c1) ??? ??? wr d1 wr d1 ??? d (d1) q (c1) d (d1) q (c1) ??? ??? q (a1) q (a1) q (b1) q (b1) wr d1 d (d1) q (c1)
rev.0.9 / dec.2000 11 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 5: mapping between colm p acket and d packet for wr command ctm/cfm col4 col3 col2 col1 col0 t 17 t 18 t 19 t 20 m a7 ma5 ma3 ma1 m=1 ma6 ma4 ma2 ma0 m b7 mb4 mb1 m b6 mb3 mb0 mb5 mb2 ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 msk (a1) retire (a1) wr a1 d (a1) act b0 act a0 transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a3 = {da,ba} t rtr t 19 t 20 t 21 t 22 ctm/cfm dqb8 dqb7 dqb1 dqb0 db71 db8 db17 db26 db35 db45 db53 db62 db7 db16 db25 db34 db44 db52 db61 db70 db1 db10 db19 db28 db37 db46 db55 db64 db0 db9 db18 db27 db36 db45 db54 db63 colm p acket prer a 2 dqa8 dqa7 ? ? ? dqa1 dqa0 d packet mb0 da71 da8 da17 da26 da35 da45 da53 da62 da7 da16 da25 da34 da44 da52 da61 da70 da1 da10 da19 da28 da37 da46 da55 da64 da0 da9 da18 da27 da36 da45 da54 da63 ma0 mb1 ma1 mb2 ma2 mb3 ma3 mb4 ma4 mb5 ma5 mb6 ma6 mb7 ma7 ? ? ? t cwd each bit of the mb7..mb0 field controls writing (=1) or no writing (=0) of the indicated db bits when the m bit of the colm p acket is one. each bit of the ma7..ma0 field controls writing (=1) or no writing (=0) of the indicated da bits when the m bit of the colm p acket is one. when m=1, the ma and mb fields c ontrol w riting of individual data bytes. when m=0, all data bytes are written unconditionally.
12 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary row-to-row packet interaction figure 6: shows two packets on the row pins separated by an interval t rrdelay which depends upon the packet contents. no other row packets are sent to banks {ba,ba+1,ba-1} between packet ?a? and packet ?b? unless noted otherwise. table9 summarizes the t rrdelay values for all possible cases. cases rr1 through rr4 show two successive act commands. in case rr1, there is no restriction since the act commands are to different devices. in case rr2, the t rr restriction applies to the same device with non-adjacent banks. cases rr3 and rr4 are illegal (as shown) since bank ba needs to be precharged. if a prer to ba, ba+1, or ba-1 is inserted, t rrdelay is t rc (t ras to the prer command, and t rp to the next act). cases rr5 through rr8 show an act command followed by a prer command. in cases rr5 and rr6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. in cases rr7 and rr8, the t ras restriction means the activated bank must wait before it can be precharged. cases rr9 through rr12 show a prer command followed by an act command. in cases rr9 and rr10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. rr10a and rr10b depend upon whether a bracketed bank (ba+-1) is precharged or activated. in cases rr11 and rr12, the same and adjacent banks must all wait t rp for the sense amp and bank to precharge before being activated. figure 6: row- to- row p acket interaction- timing ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 transaction a: r opa transaction b: r opb a0 = {da,ba,ra} b0= {db,bb,rb} t rrdelay r opa a0 r opb b0 table 9: row- to- row p acket interaction - rules case # ropa da ba ra ropb db bb rb t rrdelay example rr1 act da ba ra act /= da xxxx x..x t packet figure 11: rr2 act da ba ra act == da /= {ba,ba+1,ba-1} x..x t rr figure 11: rr3 act da ba ra act == da == { ba+1,ba-1} x..x t rc - illegal unless prer to ba/ba+1/ba-1 figure 10: rr4 act da ba ra act == da == {ba} x..x t rc - illega l unless prer to ba/ba+1/ba-1 figure 10: rr5 act da ba ra prer /= da xxxx x..x t packet figure 11: rr6 act da ba ra prer == da /= {ba,ba+1,ba-1} x..x t packet figure 11: rr7 act da ba r a prer == da == { ba+1,ba-1} x..x t ras figure 10: rr8 act da ba ra prer == da == {ba} x..x t ras figure 15: rr9 prer da ba ra act /= da xxxx x..x t packet figure 12: rr10 prer da ba ra act == da /= { ba,ba+-1,ba+-2} x..x t packet figure 12: rr10 a prer da ba ra act == da == { b a +2} x..x t packe t /t rp if ba+1 is precharged/activated. rr10 b prer da ba ra act == da == { b a -2} x..x t packet /t rp if ba-1 is precharged/activated. rr11 prer da ba ra act == da == {ba+1,ba-1} x..x t rp figure 10: rr12 prer da ba ra act == da == {ba} x..x t rp figure 10: rr13 prer da ba ra prer /= da xxxx x..x t packet figure 12: rr14 prer da ba ra prer == da /= {ba,ba+1,ba-1} x..x t pp figure 12: rr15 prer da ba ra prer == da == {ba+1,ba-1} x..x t pp figure 12: rr16 prer da ba ra prer == da == ba x..x t pp figure 12:
rev.0.9 / dec.2000 13 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary row-to-row interaction - contin- ued cases rr13 through rr16 summarize the combinations of two successive prer commands. in case rr13 there is no restriction since two devices are addressed. in rr14, t pp applies, since the same device is addressed. in rr15 and rr16, the same bank or an adjacent bank may be given repeated prer commands with only the t pp restriction. two adjacent banks can?t be activate simultaneously. a precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). if bank ba is activate and a prer is directed to ba, then bank ba will be precharged along with sense amps ba-1/ba and ba/ba+1. if bank ba+1 is activate and a prer is directed to ba, then bank ba+1 will be precharged along with sense amps ba/ba+1 and ba+1/ba+2. if bank ba-1 is activate and a prer is directed to ba, then bank ba-1 will be precharged along with sense amps ba/ba-1 and ba-1/ba-2. a row packet may contain commands other than act or prer. the refa and refp commands are equivalent to act and prer for interaction analysis purposes. the inter- action rules of the napr, naprc, pdnr, rlxr, attn, tcal, and tcen commands are discussed in later sections (see table6 for cross-ref). row-to-col packet interaction figure 7: shows two packets on the row and col pins. they must be separated by an interval t rcdelay which depends upon the packet contents. table10 summarizes the t rcdelay values for all possible cases. note that if the col packet is earlier than the row packet, it is considered a col-to-row packet interaction. cases rc1 through rc5 summarize the rules when the row packet has an act command. figure 15: and figure 16: show examples of rc5 - an activation followed by a read or write. rc4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). in cases rc1, rc2, and rc3, there is no inter- action of the row and col packets. cases rc6 through rc8 summarize the rules when the row packet has a prer command. there is either no inter- action (rc6 through rc9) or an illegal situation with a read or write of a precharged bank (rc9). the col pins can also schedule a precharge operation with a rda, wra, or prec command in a colc packet or a prex command in a colx packet. the constraints of these precharge operations may be converted to equivalent prer command constraints using the rules summarized in figure 14:. figure 7: row- to- col p acket interaction- timing ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 transaction a: r opa transaction b: copb a0 = {da,ba,ra} b1= {db,bb,cb1} t rcdelay r opa a0 copb b1 table 10: row- to- col p acket interaction - rules case # ropa da ba ra copb db bb cb1 t rcdelay example rc1 act da ba ra nocop,rd,wr /= da xxxx x..x 0 rc2 act da ba ra nocop == da xxxx x..x 0 rc3 act da ba ra rd,wr == da /= {ba,ba+1,ba-1} x..x 0 rc4 act da ba ra rd,wr == da == {ba+1,ba-1} x..x illegal r c5 act da ba ra rd,wr == da == ba x..x t rcd figure 15: rc6 prer da ba ra nocop,rd,wr /= da xxxx x..x 0 rc7 prer da ba ra nocop == da xxxx x..x 0 rc8 prer da ba ra rd,wr == da /= {ba,ba+1,ba-1} x..x 0 rc9 prer da ba ra rd,wr == da == {ba+1,ba-1} x..x illegal
14 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary col-to-col packet interaction figure 8: shows three arbitrary packets on the col pins. packets ?b? and ?c? must be separated by an interval t ccdelay which depends upon the command and address values in all three packets. table11 summarizes the t ccdelay values for all possible cases. cases cc1 through cc5 summarize the rules for every situ- ation other than the case when copb is a wr command and copc is a rd command. in cc3, when a rd command is followed by a wr command, a gap of t cac -t cwd must be inserted between the two col packets. see figure 4: for more explanation of why this gap is needed. for cases cc1, cc2, cc4, and cc5, there is no restriction (t ccdelay is t cc ). in cases cc6 through cc10, copb is a wr command and copc is a rd command. the t ccdelay value needed between these two packets depends upon the command and address in the packet with copa. in particular, in case cc6 when there is wr-wr-rd command sequence directed to the same device, a gap will be needed between the packets with copb and copc. the gap will need a colc packet with a nocop command directed to any device in order to force an automatic retire to take place. figure 18: (right) provides a more detailed explanation of this case. cases cc7, cc8, and cc9 have no restriction (t ccdelay is t cc ). for the purposes of analyzing col-to-row interactions, the prec, wra, and rda commands of the colc packet are equivalent to the nocop, wr, and rd commands. these commands also cause a precharge operation prec to take place. this precharge may be converted to an equiva- lent prer command on the row pins using the rules summarized in figure 14:. figure 8: col- to- col p acket interaction- timing ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 copa a1 transaction a: copa copc c1 transaction b: copb transaction c: copc a1 = {da,ba,ca1} b1 = {db,bb,cb1} c1 = {dc,bc,cc1} t ccdelay copb b1 table 11: col- to- col p acket interaction - rules case # copa da ba ca1 copb db bb cb1 copc d c bc cc1 t ccdelay example cc1 xxxx xxxxx x..x x..x nocop db bb cb1 xxxx xxxxx x..x x..x t cc cc2 xxxx xxxxx x..x x..x rd,wr db bb cb1 nocop xxxxx x..x x..x t cc cc3 xxxx xxxxx x..x x..x rd db bb cb1 wr xxxxx x..x x..x t cc +t cac - t cwd figure 4: cc4 xxxx xxxxx x..x x..x rd db bb cb1 rd xxxxx x..x x..x t cc figure 15: cc5 xxxx xxxxx x..x x..x wr db bb cb1 wr xxxxx x..x x..x t cc figure 16: cc6 wr == db x x..x wr db bb cb1 rd == db x..x x..x t rtr figure 18: cc7 wr == db x x..x wr db bb cb1 rd /= db x..x x..x t cc cc8 wr /= db x x..x wr db bb cb1 rd == db x..x x..x t cc cc9 nocop == db x x..x wr db bb cb1 rd == db x..x x..x t cc cc10 rd == db x x..x wr db bb cb1 rd == db x..x x..x t cc
rev.0.9 / dec.2000 15 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary col-to-row packet interaction figure 9: shows arbitrary packets on the col and row pins. they must be separated by an interval t crdelay which depends upon the command and address values in the packets. table12 summarizes the t crdelay value for all possible cases. cases cr1, cr2, cr3, and cr9 show no interaction between the col and row packets, either because one of the commands is a nop or because the packets are directed to different devices or to non-adjacent banks. case cr4 is illegal because an already-activated bank is to be re-activated without being precharged case cr5 is illegal because an adjacent bank can?t be activated or precharged until bank ba is precharged first. in case cr6, the colc packet contains a rd command, and the row packet contains a prer command for the same bank. the t rdp parameter specifies the required spacing. likewise, in case cr7, the colc packet causes an auto- matic retire to take place, and the row packet contains a prer command for the same bank. the t rtp parameter specifies the required spacing. case cr8 is labeled ?hazardous? because a wr command should always be followed by an automatic retire before a precharge is scheduled. figure 19: shows an example of what can happen when the retire is not able to happen before the precharge. for the purposes of analyzing col-to-row interactions, the prec, wra, and rda commands of the colc packet are equivalent to the nocop, wr, and rd commands. these commands also cause a precharge operation to take place. this precharge may converted to an equivalent prer command on the row pins using the rules summarized in figure 14:. a row packet may contain commands other than act or prer. the refa and refp commands are equivalent to act and prer for interaction analysis purposes. the inter- action rules of the napr, pdnr, and rlxr commands are discussed in a later section. figure 9: col- to- row p acket interaction- timing ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t t 17 t 18 t 19 transaction a: copa transaction b: r opb a1= {da,ba,ca1} b0= {db,bb,rb} t crdelay r opb b0 copa a1 table 12: col- to- row p acket interaction - rules case # copa da ba ca1 ropb db bb rb t crdelay example cr1 nocop da ba ca1 x..x xxxxx xxxx x..x 0 cr2 rd/wr da ba ca1 x..x /= da xxxx x..x 0 cr3 rd/wr da ba ca1 x..x == da /= {ba,ba+1,ba-1} x..x 0 cr4 rd/wr da ba ca1 act == da == {ba} x..x illegal cr5 rd/wr da ba ca1 x..x == da == {ba+1,ba-1} x..x illegal cr6 rd da ba ca1 prer == da == {ba,ba+1,ba-1} x..x t rdp figure 15: cr7 retire a da ba ca1 prer == da == {ba,ba+1,ba-1} x..x t rtp figure 16: cr8 wr b da ba ca1 prer == da == {ba,ba+1,ba-1} x..x 0 figure 19: cr9 xxxx da ba ca1 norop xxxxx xxxx x..x 0 a. this is any command which permits the write buffer of device da to retire (see table7). ?ba? is the bank address in the write bu ffer. b. this situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. see figure 19 :.
16 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary row-to-row examples figure 10: shows examples of some of the the row-to- row packet spacings from table9. a complete sequence of activate and precharge commands is directed to a bank. the rr8 and rr12 rules apply to this sequence. in addition to satisfying the t ras and t rp timing parameters, the separa- tion between act commands to the same bank must also satisfy the t rc timing parameter (rr4). when a bank is activated, it is necessary for adjacent banks to remain precharged. as a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the rr11 and rr3 rules are analogous to the rr12 and rr4 rules. figure 11: shows examples of the act-to-act (rr1, rr2) and act-to-prer (rr5, rr6) command spacings from table9. in general, the commands in row packets may be spaced an interval t packet apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both prer or both act) directed to the same device. figure 10: row packet e xample ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prer a1 t ras t rc a0 = {da,ba,ra} a1 = {da,ba +1 } b0 = {da,ba+1,rb} same device adjacent b ank rr 7 t rp same device adjacent b ank rr11 act b0 b0 = {da,ba,rb} same device same bank rr12 b0 = {da,ba+1,rb} same device adjacent b ank rr 3 b0 = {da,ba,rb} same device same bank rr 4 figure 11: row packet e xample ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prer b0 t packet act c0 t rr a0 = {da,ba,ra} b0 = {db,bb,rb} c0 = {da,bc,rc} different d evice any b ank same device non-adjacent b ank rr 1 rr 2 act a0 act a0 act b0 prer c0 b0 = {db,bb,rb} c0 = {da,bc,rc} different d evice any b ank same device non-adjacent b ank rr5 rr 6 act a0 t packet t packet
rev.0.9 / dec.2000 17 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 12: shows examples of the prer-to-prer (rr13, rr14) and prer-to-act (rr9, rr10) command spacings from table9. the rr15 and rr16 cases (prer-to-prer to same or adjacent banks) are not shown, but are similar to rr14. in general, the commands in row packets may be spaced an interval t packet apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both prer or both act) directed to the same device. row and column cycle description activate: a row cycle begins with the activate (act) opera- tion. the activation process is destructive; the act of sensing the value of a bit in a bank?s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. restore: because the activation process is destructive, a hidden operation called restore is automatically performed. the restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. read/write: while the restore operation takes place, the sense amp may be read (rd) and written (wr) using column operations. if new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. precharge: when both the restore operation and the column operations are completed, the sense amp and bank are precharged (pre). this leaves them in the proper state to begin another activate operation. intervals: the activate operation requires the interval t rcd,min to complete. the hidden restore operation requires the interval t ras,min - t rcd,min to complete. column read and write operations are also performed during the t ras,min - t rcd,min interval (if more than about four column opera- tions are performed, this interval must be increased). the precharge operation requires the interval t rp,min to complete. adjacent banks: an rdram with a ?s? designation (512kx32sx16/18) indicates it contains ?split banks?. this means the sense amps are shared between two adjacent banks. the only exception is that sense amp 0, 15, 16, and 31 are not shared. when a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. these two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. for example (referring to the block diagram of figure 2:), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 2kbyte row - 512 bytes to the dqa side and 512 bytes to the dqb side). while this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. figure 12: row p acket examples ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 prer a 0 act b0 t packet prer c 0 a0 = {da,ba,ra} b0 = {db,bb,rb} c0 = {da,bc,rc} different d evice any b ank same device non-adjacent b ank rr13 rr 14 prer a0 prer a 0 prer b 0 act c0 b0 = {db,bb,rb} c0 = {da,bc,rc} different d evice any b ank same device non-adjacent b ank rr9 rr 10 prer a0 c0 = {da,b a+1r c} same device same b ank rr1 6 c0 = {da,b a, rc} same device ad jacent bank rr1 5 t pp t packet t packet
18 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary precharge mechanisms figure 13: shows an example of precharge with the rowr packet mechanism. the prer command must occur a time t ras after the act command, and a time t rp before the next act command. this timing will serve as a baseline aginst which the other precharge mechanisms can be compared. figure 14: (top) shows an example of precharge with a rda command. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these commands is a rda, which causes the bank to auto- matically precharge when the final read has finished. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colc packet with the rda command. the rda command should be treated as a rd command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. figure 14: (middle) shows an example of precharge with a wra command. as in the rda example, a bank is acti- vated with an rowa packet on the row pins. then, two dualocts are written with wr commands in colc packets on the col pins. the second of these commands is a wra, which causes the bank to automatically precharge when the final write has been retired. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colc packet that causes the automatic retire. the wra command should be treated as a wr command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. note that the automatic retire is triggered by a colc packet a time t rtr after the colc packet with the wr command unless the second colc contains a rd command to the same device. this is described in more detail in figure 17:. figure 14: (bottom) shows an example of precharge with a prex command in an colx packet. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these colc packets includes an colx packet with a prec command. this causes the bank to precharge with timing equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colx packet with the prex command. figure 13: precharge via prer command in rowr packet ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prer a5 t ras t r c a0 = {da,ba,ra} a5 = {da,ba} b0 = {da,ba,rb} t r p act b0
rev.0.9 / dec.2000 19 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 14: offsets for alternate precharge mechanisms ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rd a1 act a0 rd a2 q (a2) q (a1) act b0 msk (a2) msk (a1) retire (a1) t offp wr a1 d (a2) d (a1) act b0 act a0 transaction a: rd a0 = {da,ba,ra} a5 = {da,ba} colc packet: rda precharge offset colc packet: wda precharge offset transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a5 = {da,ba} colx packet: prex precharge offset rd a3 q (a4) q (a3) rda a4 prer a5 the rda precharge is equivalent to a prer command here t offp prer a 5 the wra precharge (triggered by the automatic retire) is equivalent to a prer command here wra a2 retire (a2) t rtr a3 = {da,ba,ca3} a4 = {da,ba,ca4} a1 = {da,ba,ca1} a2 = {da,ba,ca2} rd a1 act a0 rd a2 q (a2) q (a1) act b0 t offp transaction a: rd a0 = {da,ba,ra} a5 = {da,ba} rd a3 q (a4) q (a3) prer a5 the prex precharge command is equivalent to a prer command here a3 = {da,ba,ca3} a4 = {da,ba,ca4} a1 = {da,ba,ca1} a2 = {da,ba,ca2} rd a4 prex a5
20 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary read transaction - example figure 15: shows an example of a read transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd later a rd a1 command is issued in a colc packet. note that the act command includes the device, bank, and row address (abbreviated as a0) while the rd command includes device, bank, and column address (abbreviated as a1). a time t cac after the rd command the read data dualoct q(a1) is returned by the device. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second is issued. it contains a rd a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cac after the second rd command a second read data dualoct q(a2) is returned by the device. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). the prer command must also occur a time t rdp or more after the last rd command. note that the t rdp value shown is greater than the t rdp,min specification in table 21. this transaction example reads two dualocts, but there is actually enough time to read three dualocts before t rdp becomes the limiting parameter rather than t ras . if four dualocts were read, the packet with prer would need to shift right (be delayed) by one t cycle (note - this case is not shown). finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a. figure 15: read transaction example ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rd a1 act a0 prer a 3 rd a2 q (a2) t rcd t cac t cc q (a1) act b0 t ras t rc t rp transaction a: rd a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a3 = {da,ba} t cac t rdp transaction b: xx b0 = {da,ba,rb}
rev.0.9 / dec.2000 21 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary write transaction - example figure 16: shows an example of a write transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd later a wr a1 command is issued in a colc packet. note that the act command includes the device, bank, and row address (abbreviated as a0) while the wr command includes device, bank, and column address (abbreviated as a1). a time t cwd after the wr command the write data dualoct d(a1) is issued. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second colc packet is issued. it contains a wr a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cwd after the second wr command a second write data dualoct d(a2) is issued. a time t rtr after each wr command an optional colm packet msk (a1) is issued, and at the same time a colc packet is issued causing the write buffer to automatically retire. see figure 17: for more detail on the write/retire mechanism. if a colm packet is not used, all data bytes are unconditionally written. if the colc packet which causes the write buffer to retire is delayed, then the colm packet (if used) must also be delayed. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). a prer a3 command is issued in an rowr packet on the row pins. the prer command must occur a time t rtp or more after the last colc which causes an automatic retire. finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a. figure 16: write transaction example ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 msk (a2) retire (a2) msk (a1) retire (a1) wr a1 prer a 3 wr a2 d (a2) t rcd d (a1) act b0 t rc t rp act a0 t cwd transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba,ca2} a3 = {da,ba} t cc t cwd t r tr t ras t r tr t rtp transaction b: xx b0 = {da,ba,rb}
22 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary write/retire - examples the process of writing a dualoct into a sense amp of an rdram bank occurs in two steps. the first step consists of transporting the write command, write address, and write data into the write buffer. the second step happens when the rdram automatically retires the write buffer (with an optional bytemask) into the sense amp. this two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. figure 17: (left) shows an example of this two step process. the first colc packet contains the wr command and an address specifying device, bank and column. the write data dualoct follows a time t cwd later. this information is loaded into the write buffer of the specified device. the colc packet which follows a time t rtr later will retire the write buffer. the retire will happen automatically unless (1) a colc packet is not framed (no colc packet is present and the s bit is zero), or (2) the colc packet contains a rd command to the same device. if the retire does not take place at time t rtr after the original wr command, then the device continues to frame colc packets, looking for the first that is not a rd directed to itself. a bytemask msk(a1) may be supplied in a colm packet aligned with the colc that retires the write buffer at time t rtr after the wr command. the memory controller must be aware of this two-step write/retire process. controller performance can be improved, but only if the controller design accounts for several side effects. figure 17: (right) shows the first of these side effects. the first colc packet has a wr command which loads the address and data into the write buffer. the third colc causes an automatic retire of the write buffer to the sense amp. the second and fourth colc packets (which bracket the retire packet) contain rd commands with the same device, bank and column address as the original wr command. in other words, the same dualoct address that is written is read both before and after it is actually retired. the first rd returns the old dualoct value from the sense amp before it is overwritten. the second rd returns the new dualoct value that was just written. figure 18: (left) shows the result of performing a rd command to the same device in the same colc packet slot that would normally be used for the retire operation. the read may be to any bank and column address; all that matters is that it is to the same device as the wr command. the retire operation and msk(a1) will be delayed by a time t packet as a result. if the rd command used the same bank and column address as the wr command, the old data from the sense amp would be returned. if many rd commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbi- trarily long time. however, once a rd to another device or a wr or nocop to any device is issued, the retire will take place. figure 18: (right) illustrates a situation in which the controller wants to issue a wr-wr-rd colc packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. figure 17: normal retire (left) and retire/read ordering (right) ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr a1= {da,ba,ca1} d (a1) wr a1 ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr transaction b: rd a1= {da,ba,ca1} b1= {da,ba,ca1} retire (a1) msk (a1) t rtr t cwd d (a1) wr a1 retire (a1) msk (a1) t rtr rd b1 rd c1 q (b1) t cwd transaction c: rd c1= {da,ba,ca1} t cac this rd gets the old data this rd gets the new data retire is automatic here unless: t cac (1) no colc p acket (s=0) or (2) colc p acket is rd to device da q (c1)
rev.0.9 / dec.2000 23 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary write/retire examples - continued the rd will prevent a retire of the first wr from automati- cally happening. but the first dualoct d(a1) in the write buffer will be overwritten by the second wr dualoct d(b1) if the rd command is issued in the third colc packet. therefore, it is required in this situation that the controller issue a nocop command in the third colc packet, delaying the rd command by a time of t packet . this situa- tion is explicitly shown in table11 for the cases in which t ccdelay is equal to t rtr . figure 19: shows a possible result when a retire is held off for a long time (an extended version of figure 18:-left). after a wr command, a series of six rd commands are issued to the same device (but to any combination of bank and column addresses). in the meantime, the bank ba to which the wr command was originally directed is precharged, and a different row rc is activated. when the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. the controller can insure that this doesn?t happen by never precharging a bank with an unretired write buffer. note that in a system with more than one rdram, there will never be more than two rdrams with unretired write buffers. this is because a wr command issued to one device automatically retires the write buffers of all other devices written a time t rtr before or earlier. figure 18: retire held off by read (left) and controller forces wwr gap (right) ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 transaction a: wr transaction b: rd a1= {da,ba,ca1} b1= {da,bb,cb1} transaction a: wr transaction b: wr a1= {da,ba,ca1} b1= {da,bb,cb1} d (a1) wr a1 retire (a1) msk (a1) rd b1 q (b1) t cwd t cac ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 18 t 19 d (a1) wr a1 rd c1 t rtr retire (a1) msk (a1) t cwd t cac wr b1 d (b1) transaction c: rd c1= {da,bc,cc1} the controller must insert a nocop to retire (a1) to make room for the data (b1) in the write buffer the retire operation for a write can be held off by a read to the same device t rtr + t packet figure 19: retire held off by reads to same device, write buffer retired to new row ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 msk (a1) retire (a1) rd b1 wr a1 prer a 2 t rcd act c0 t ras t rc t rp act a0 t cwd t rtr transaction a: wr a0 = {da,ba,ra} a1 = {da,ba,ca1} a2 = {da,ba} rd b2 rd b3 rd b4 rd b5 rd b6 transaction b: rd b1 = {da,bb,cb1} b2 = {da,bb,cb2} b3= {da,bb,cb3} b4 = {da,bb,cb4} b5 = {da,bb,cb5} b6 = {da,bb,cb6} q (b1) t cac q (b2) q (b3) q (b4) q (b5) transaction c: wr c0 = {da,ba,rc} d (a1) the retire operation puts the write data in the new row warning this sequence is hazardous and must be used with caution
24 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary interleaved write - example figure 20: shows an example of an interleaved write transac- tion. transactions similar to the one presented in figure 16: are directed to non-adjacent banks of a single rdram. this allows a new transaction to be issued once every t rr interval rather than once every t rc interval (four times more often). the dq data pin efficiency is 100% with this sequence. with two dualocts of data written per transaction, the col, dqa, and dqb pins are fully utilized. banks are precharged using the wra autoprecharge option rather than the prer command in an rowr packet on the row pins. in this example, the first transaction is directed to device da and bank ba. the next three transactions are directed to the same device da, but need to use different, non-adjacent banks bb, bc, bd so there is no bank conflict. the fifth transaction could be redirected back to bank ba without interference, since the first transaction would have completed by then (t rc has elapsed). each transaction may use any value of row address (ra, rb, ..) and column address (ca1, ca2, cb1, cb2, ...). interleaved read - example figure 21: shows an example of interleaved read transac- tions. transactions similar to the one presented in figure 15: are directed to non-adjacent banks of a single rdram. the address sequence is identical to the one used in the previous write example. the dq data pins efficiency is also 100%. the only difference with the write example (aside from the use of the rd command rather than the wr command) is the use of the prex command in a colx packet to precharge the banks rather than the rda command. this is done because the prex is available for a readtransaction but is not available for a masked write transaction. interleaved rrww - example figure 22: shows a steady-state sequence of 2-dualoct rd/rd/wr/wr.. transactions directed to non-adjacent banks of a single rdram. this is similar to the interleaved write and read examples in figure 20: and figure 21: except that bubble cycles need to be inserted by the controller at read/write boundaries. the dq data pin efficiency for the example in figure 22: is 32/42 or76%. if there were more rdrams on the channel, the dq pin efficiency would approach 32/34 or 94% for the two-dualoct rrww sequence (this case is not shown). in figure 22:, the first bubble type t cbub1 is inserted by the controller between a rd and wr command on the col pins. this bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in figure 4:. this bubble appears on the dqa and dqb pins as t dbub1 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub1 . figure 20: interleaved write transaction with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 msk (b2) wra c2 msk (b1) wr c1 wr b1 msk (a1) wra b2 msk (a2) d (b2) d (b1) act b0 act c0 act d0 act e0 d (a2) d (a1) wr d1 msk (c1) d(c1) act f0 wr d2 msk (c2) wr e1 msk (d1) d (c2) d (d1) wr e2 msk (d2) d (z2) d (z1) d (x2) d (y1) d (y2) msk (z2) wra a2 msk (z1) wr a1 wr z1 msk (y1) wra z2 msk (y2) q (d1) t rcd t cwd t rc transaction e can use the same bank as transaction a t rr f3 = {da,ba +2 } transaction f: wr f0 = {da,b a+2,rf} f1 = {da,b a+2, c f1} f2= {da,b a+2, c f2} e3 = {da,ba} transaction e: wr e0 = {da,b a,re} e1 = {da,b a, c e1} e2= {da,b a, c e2} d3 = {da,ba +6 } transaction d: wr d0 = {da,b a+6,rd} d1 = {da,b a+6, c d1} d2= {da,b a+6, c d2} c3 = {da,ba +4 } transaction c: wr c0 = {da,b a+4,rc} c1 = {da,b a+4, c c1} c2= {da,b a+4, c c2} b3 = {da,ba +2 } transaction b: wr b0 = {da,b a+2,rb} b1 = {da,b a+2, c b1} b2= {da,b a+2, c b2} a3 = {da,ba} transaction a: wr a0 = {da,b a,ra} a1 = {da,b a, c a1} a2= {da,b a, c a2} z3 = {da,ba +6 } transaction z: wr z0 = {da,b a+6,rz} z1 = {da,b a+6, c z1} z2= {da,b a+6, c z2} y3 = {da,ba +4 } transaction y: wr y0 = {da,b a+4,ry} y1 = {da,b a+4, c y1} y2= {da,b a+4, c y2}
rev.0.9 / dec.2000 25 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary the second bubble type t cbub2 is inserted (as a nocop command) by the controller between a wr and rd command on the col pins when there is a wr-wr-rd sequence to the same device. this bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in figure 18:. there would be no bubble if address c0 and address d0 were directed to different devices. this bubble appears on the dqa and dqb pins as t dbub2 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub2 . figure 21: interleaved read transaction with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 prex b 3 rd c2 rd c1 rd b1 rd b2 prex a 3 act b0 act c0 act d0 act e0 rd a1 rd a2 prex z 3 rd d1 act f0 rdd2 prex c 3 rd e1 rd e2 prex d 3 rd z1 rd z2 prex y 3 q (b2) q (b1) q (a2) q (a1) q (c1) q (c2) q (d1) q (z2) q (z1) q (x2) q (y1) q (y2) t rcd t cac transaction e can use the same bank as transaction a t rc t rr f3 = {da,ba +2 } transaction f: rd f0 = {da,b a+2,rf} f1 = {da,b a+2, c f1} f2= {da,b a+2, c f2} e3 = {da,ba} transaction e: rd e0 = {da,b a,re} e1 = {da,b a, c e1} e2= {da,b a, c e2} d3 = {da,ba +6 } transaction d: rd d0 = {da,b a+6,rd} d1 = {da,b a+6, c d1} d2= {da,b a+6, c d2} c3 = {da,ba +4 } transaction c: rd c0 = {da,b a+4,rc} c1 = {da,b a+4, c c1} c2= {da,b a+4, c c2} b3 = {da,ba +2 } transaction b: rd b0 = {da,b a+2,rb} b1 = {da,b a+2, c b1} b2= {da,b a+2, c b2} a3 = {da,ba} transaction a: rd a0 = {da,b a,ra} a1 = {da,b a, c a1} a2= {da,b a, c a2} z3 = {da,ba +6 } transaction z: rd z0 = {da,b a+6,rz} z1 = {da,b a+6, c z1} z2= {da,b a+6, c z2} y3 = {da,ba +4 } transaction y: rd y0 = {da,b a+4,ry} y1 = {da,b a+4, c y1} y2= {da,b a+4, c y2} figure 22: interleaved rrww sequence with two dualoct data length ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 act a0 msk (b2) wra c2 msk (b1) wr c1 wr b1 msk (y2) wra b2 prex a 3 d (b2) d (b1) act b0 act c0 act d0 act e0 rd a1 rd a2 prex z 3 q (a2) q (a1) msk (c1) d (c1) nocop msk (c2) rdd 0 d (c2) t rbub1 rdf1 q (z2) q (z1) d (y 2) rd z1 rd z2 t cbub1 t dbub1 t dbub1 t dbub2 t cbub2 t rbub2 t cbub2 nocop transaction e can use the same bank as transaction a f3 = {da,ba+2} transaction f: wr f0 = {da,ba+2,rf} f1 = {da,ba+2,cf1} f2= {da,ba+2,cf2} e3 = {da,ba} transaction e: rd e0 = {da,ba,re} e1 = {da,ba,ce1} e2= {da,ba,ce2} d3 = {da,ba+6} transaction d: rd d0 = {da,ba+6,rd} d1 = {da,ba+6,cd1} d2= {da,ba+6,cd2} c3 = {da,ba+4} transaction c: wr c0 = {da,ba+4,rc} c1 = {da,ba+4,cc1} c2= {da,ba+4,cc2} b3 = {da,ba+2} transaction b: wr b0 = {da,ba+2,rb} b1 = {da,ba+2,cb1} b2= {da,ba+2,cb2} a3 = {da,ba} transaction a: rd a0 = {da,ba,ra} a1 = {da,ba,ca1} a2= {da,ba,ca2} z3 = {da,ba+6} transaction z: rd z0 = {da,ba+6,rz} z1 = {da,ba+6,cz1} z2= {da,ba+6,cz2} y3 = {da,ba+4} transaction y: wr y0 = {da,ba+4,ry} y1 = {da,ba+4,cy1} y2= {da,ba+4,cy2}
26 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary control register transactions the rdram has two cmos input pins sck and cmd and two cmos input/output pins sio0 and sio1. these provide serial access to a set of control registers in the rdram. these control registers provide configuration information to the controller during the initialization process. they also allow an application to select the appropriate operating mode of the rdram. sck (serial clock) and cmd (command) are driven by the controller to all rdrams in parallel. sio0 and sio1 are connected (in a daisy chain fashion) from one rdram to the next. in normal operation, the data on sio0 is repeated on sio1, which connects to sio0 of the next rdram (the data is repeated from sio1 to sio0 for a read data packet). the controller connects to sio0 of the first rdram. write and read transactions are each composed of four packets, as shown in figure 23: and figure 24:. each packet consists of 16 bits, as summarized in table13 and table14. the packet bits are sampled on the falling edge of sck. a transaction begins with a srq (serial request) packet. this packet is framed with a 11110000 pattern on the cmd input (note that the cmd bits are sampled on both the falling edge and the rising edge of sck). the srq packet contains the sop3..sop0 (serial opcode) field, which selects the trans- action type. the sdev4..sdev0 (serial device address) selects one of the 32 rdrams. if sbc (serial broadcast) is set, then all rdrams are selected. the sa (serial address) packet contains a 12 bit address for selecting a control register. a write transaction has a sd (serial data) packet next. this contains 16 bits of data that is written into the selected control register. a sint (serial interval) packet is last, providing some delay for any side-effects to take place. a read transaction has a sint packet, then a sd packet. this provides delay for the selected rdram to access the control register. the sd read data packet travels in the oppo- site direction (towards the controller) from the other packet types. because the rdram drivers data on the falling sck edge,the read data transmit windows is offset tscycle/2 relative to the other packet types.the sck cycle time will accomodate the total delay. figure 23: seri al w rite (swr) transaction to control register sr q - swr command 1111 00000000...00000000 sr q - swr command 0000 sa sa sd sd sint sint 00000000...00000000 00000000...00000000 00000000...00000000 sck cmd si o0 s i o1 t 4 t 3 6 t 20 t 52 t 6 8 each packet is repeated from sio0 to sio1 1 1 1 1 0 0 0 0 1111 next transaction figure 24: seri al r ead (srd) transaction control register sr q - srd command 1111 00000000...00000000 sr q - srd command 0000 sa sa sint sint sd sd 00000000...00000000 00000000...00000000 00000000...00000000 sck cmd sio0 sio1 t 4 t 3 6 t 20 t 52 t 6 8 first 3 packets are repeated from sio0 to sio1 non-addressed rdrams pass 0/sd15..sd0/0 from sio1 to sio0 1 1 1 1 0 0 0 0 1111 next transaction 0 0 controller drives sint15..sint0 / 17*z/0 on sio0 0 0 addressed rdram drives 0/sd15..sd0/0 on sio0
rev.0.9 / dec.2000 27 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary control register packets table13 summarizes the formats of the four packet types for control register transactions. table14 summarizes the fields that are used within the packets. figure 25: shows the transaction format for the setr, clrr, and setf commands. these transactions consist of a single srq packet, rather than four packets like the swr and srd commands. the same framing sequence on the cmd input is used, however. figure 25: setr , c lrr ,setf transaction sck cmd sio0 t 20 sr q packet - setr/clrr/setf 1111 00000000 ... 00000000 srq packet - setr/clrr/setf 0000 sio1 t 4 the packet is repeated from sio0 to sio1 1 1 1 1 0 0 0 0 table 13: control register packet formats sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd 0 rsrv rsrv 0 sd15 8 sop1 sa7 0 sd7 1 rsrv rsrv 0 sd14 9 sop0 sa6 0 sd6 2 rsrv rsrv 0 sd13 10 sbc sa5 0 sd5 3 rsrv rsrv 0 sd12 11 sdev4 sa4 0 sd4 4 rsrv sa11 0 sd11 12 sdev3 sa3 0 sd3 5 sdev5 sa10 0 sd10 13 sdev2 sa2 0 sd2 6 sop3 sa9 0 sd9 14 sdev1 sa1 0 sd1 7 sop2 sa8 0 sd8 15 sdev0 sa0 0 sd0 table 14: field description for control register packets field description rsrv reserved. should be driven as ?0? by controller. sop3..sop0 0000 - srd. serial read of control register {sa11..sa0} of rdram {sdev5..sdev0}. 0001 - swr. serial write of control register {sa11..sa0} of rdram {sdev 5..sdev0}. 0010 - setr. set reset bit, all control registers assume their reset values. a must be followed by a delay and a clrr b 0100 - setf. set fast (normal) clock mode. 4 t scycle delay until clrr command 1011 - clrr. clear reset bit, all control registers retain their reset values. a 4 t scycle delay until next command. 1111 - nop. no serial operation. 0011, 0101-1010, 1100-1110 - rsrv. reserved encodings. sdev5..sdev0 serial device. compared to sdevid 5..sdevid0 field of init control register field to select the rdram to which the trans- action is directed. sbc serial broadcast. when set, rdrams ignore {sdev 5..sdev0} for rdram selection. sa11..sa0 serial address. selects which control register of the selected rdram is read or written. sd15..sd0 serial data. the 16 bits of data written to or read from the selected control register of the selected rdram. a. the setr and clrr commands must always be applied in two successive transactions to rdrams; i.e. they may not be used in isol ation. this is called ? setr/clrr reset ?. b. a minimum gap equal to the larger of {16 * t scycle , 2816 * t cycle } must be inserted between a setr / clrr command pair.
28 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary initialization initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. the controller prepares the rdram sub-system for normal channel operation by using a sequence of control register transactions on the serial cmos pins. the following subsystem compo- nents(including the rdram components)during initialization. this sequence is available in the form of reference code. 1.0 start clocks - this step calculates the proper clock frequencies for pc1k(controller logic), sync1k(rac block), refc1k(drcg component), ctm(rdram component) and sck(sio block) 2.0 rac initialization - this step causes the init block to generate a rac, performs rac maintainance operations and measures timing intervals in order to ensure clock stability. 3.0 rdram initialization - this stage performs most of the steps needed to rdrams. the rest are performed in stages 5.0, 6.0 and 7.0. all of the steps in3.0 are carried out through the sio block interface. o 3.1/3.2 sio reset - this reset operation is performed before any sio control register read or write transac- tions. it clears six registers (test34, cca, ccb, skip, test78 and test79) and places the init register into a special state (all bits cleares except skp and sdevid fields are set to ones). cmd and sio must be held low until sioreset. o 3.3 write test77 register - test77 register must be explicitly written with zeros bdfore any other registers are read or written. o 3.4 write tcycle register - the tcycle register is written with the ctm clock(for channel and rdrams) in units of 64ps. the tcycle value is determined in stage 1.0. o 3.5 write sdevid register - the sdevid (serial device identification) register of each rdram is written with a unique address value so that directed sio read and write trans- actions can be performed. this address value increases form 0 to 31 according to the distance an rdram is from the asic component on the sio bus(the closest rdram is address 0). o 3.6 write devid register - the devid (device identifica- tion) register of each rdram is written with a unique address value so that directed memory read and write transactions can be performed. this address value increases from 0 to 31. the devid value is not necessarily the same as the rdrams are sorted into regions of the same core configuration (number of bank, row and column address bits and core type). o 3.7 write pdnx, pdnxa registers - the pdnx and pdnxa registers are written with values that are used to measure the timing intervals connected with an exit from the pdn(powerdown) power state. o 3.8 write napx register - the napx register is written with values that are used to measure the timing intervals connected with an exit from the nap power state. o3.9 write tparm register - the tparm register is written with values whitch determine the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the values written set each rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. o 3.10 write tcdly1 register - the tcdly1 register is written with values which determine the time interval between a col packet with a memory read command and thd qpacket with the read data on the channel . the values written set each rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. o 3.11 write tfrm register - the tfrm register is written with a value trdc parameter is the time interval between a row packet with an activate command and the col packet with a read or write command. o 3.12 setr / clrr - first write the following registers with the indicated values: test78 <= 0004 16 test34 <= 0040 16 next, each rdram is given a setr command and a clrr command through the sio block. this sequence performs a second reset operation on the rdrams. then the test34 and test78 registers are rewritten with zero, in that order. figure 26 : sio reset sequence sck cmd s i o0 t 16 0000000000000000 0000000 0 .. . 00000000 0000000000000000 1100 si o1 t 0 the packet is repeated from sio0 to sio1 1 1 1 1 0 0 0 0
rev.0.9 / dec.2000 29 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary o 3.13 write cca and ccb register - these registers are written with a value halfway between their minimum and maximum values. this shortens the time needed for the rdrams to reach their steady-state current control values in stage 5.0. o 3.14 powerdown exit - the rdrams are in the pdn power state at this point . abroadcast pdnexit command is performed by the sio block to place the rdrams in the rlx(relax) power state in which they are ready to receive row packets. o 3.15 setf - each rdram is given a setf command through teh sio block. one of the operations performed by this step is to generate a value skip register and fix the rdram to particular read domain. 4.0 controller configuration - this stage initializes the controller block. each step of this stae will set a field of the confi- grmc[63:0] bus to the appropriate value. other controller imple- mentations will have similar initialization requirements and this stage may be used as a guide. o 4..1 initial read data offsets - the configrmc bus is written with a ol packet with a memory read command and the qpacket with the read data on the channel. the value written sets rmc.d1 to the minimum value permitted for the system. the will be adjusted later in stage 6.0. o 4.2 configure row/column timing - this step determines the values of the tras,min, trp,min, trc,min, trcd,min, trr,min and tpp,min rdram timing parameters that are present in the system. the configrmc bus is written with values that will be compatible with all rdram devices that are present. o 4.3 set refresh interval - this step determines the values of the tref, max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. o 4.4 set current control interval - this step determines the values of the tcctrl,max rdram timing parameter that are present in the system. the configrmc bus is written with value that will be compatible with all rdram devices that are presnet. o 4.5 set slew rate control interval - this step determines the values of the ttemp,max rdram timing parameter that are present ing the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. o 4.6set bank/rcol addressbits - this step deterimines the number of rdram bank, row and column address bits that are present in the system. it also determines the rdram core types (independent, doubled or split) that are present. the configrmc bus is written with a value that will be compatiblel with all rdram devices that are present. 5.0 rdram current control - this step causes the init block to generate a sequence of pulses which performs rdram mainte- nance operations. 6.0 rdram core, read domain initialization - this stage completes the rdram initialization. o 6.1 rdram core initialization - a sequence of 192memory refresh transctions is performed in order to place the cores of all rdrams into the proper operating state. o 6.2 rdram read domain initialization - a memory write and memory read transaction is performed to each rdram to determine which read domain each rdram occupies. the programmed delay of each rdram is then adjusted do the total rdram read delay (propagation delay plus programmed delayp is constant. the tparm and tcdlyi registers of each rdram are rewritten with the appropriate read delay values. the configrmc bus is also rewritten with an updated value. 7.0 other rdram register fields - this stage rewrites the init register with the final values of the lsr, nsr and psr fields. in essence, the conroller must read all the read-only configuration registers of all rdrams (or it must read the spd device present on each rimm), it must process this information and then it must write all the read-write registers to place the rdrams into the proper operating mode. initialization note [1] : during the initialization process, it is necessary for the controller to preform 128 current control opera- tions (3xcal, 1xcal/sam) and one temperature calibrate opera- tion (tcen/tcal) after reset or after power down (pdn) exit. initialization note [2] : there are two classes of 64/72mbit rdram. they are distinguished by the ?s28ieco? bit in the spd. the behavior of the rdram at initialization is slightly different for the two types: s28ieco=0: upon powerup the device enters attn state. the serial operdevid match of the sbc bit (broadcast) to be set. s28ieco=1: upon powerup the device enters pdn state. the serial operations setr, clrr and setf require a sdevid match. see the document detailing the reference initialization procedure for more information on how to handle this in a system. initialization note [3] : after the step of equalizing the total read delay of eac rdram has been completed (i.e. after the tcdly0
30 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary and tcdly1 fields have been written for the final time), a single final memory read transaction shoujd be made to each rdrzm in order to ensure that the output pipeline stages have been cleared. initialization note [4] : the setf command (in the serial srq packet) should only be issued once during the initialization process ad should the setr and clrr commands. initialization note [5] : the clrr command (in the serial srq packet) leqves some of the contents of the memory core in an inde- terminate state. control register summary table15 summarizes the rdram control registers. detail is provided for each control register in figure 27: through figure 43:. read-only bits which are shaded gray are unused and return zero. read-write bits which are shaded gray are reserved and should always be written with zero. the rimm spd application note (dl-0054) describes additional read- only configuration registers which are present on direct rimms. the state of the register fields are potentially affected by the io reset operation or the setr/clrr operation. this is indicated in the text accompanying each register diagram. table 15: control register summary sa11..sa 0 registe r fiel d read-write / r ead-only descriptio n 021 16 init sdevid read-write, 6 b its serial device id. device address for control register read/write. psx read-write, 1 bit power select exit. pdn/nap exit with device addr on dqa5..0. srp read-write, 1 bit sio repeater. used to initialize rdram. nsr read-write, 1 bit nap self-refresh. enables self-refresh in nap mode. psr read-write, 1 bit pdn self-refresh. enables self-refresh in pdn mode. lsr read-write, 1 bit low power self-refresh. enables low power self-refresh. ten read-write, 1 bit temperature sensing enable. tsq read-write, 1 bit temperature sensing output. dis read-write, 1 bit rdram disable. 0 22 1 6 test34 test34 read-write, 1 6 b its test register. 0 23 1 6 cnfga refbit read-only, 3 bit refresh bank bits. used for multi-bank refresh. dbl read-only, 1 bit double. specifies doubled-bank architecture mver read-only, 6 bit manufacturer version. manufacturer identification number. pver read-only, 6 bit protocol version. specifies version of direct protocol supported. 0 24 1 6 cnfgb byt read-only, 1 bit byte. specifies an 8-bit or 9-bit byte size. devtyp read-only, 3 bit device type. device can be rdram or some other device category. spt read-only, 1 bit split-core. each core half is an individual dependent core. corg read-only, 6 bit core organization. bank, row, column address field sizes. sver read-only, 6 bit stepping version. mask version number. 040 16 devid devid read-write, 5 bits device id. device address for memory read/write. 041 16 refb refb read-write, 5bits refresh bank. next bank to be refreshed by self-refresh. 042 16 refr refr read-write, 9 bits refresh row. next row to be refreshed by refa, self-refresh. 043 16 cca cca read-write, 7 bits current control a. controls i ol output current for dqa. asyma read-write, 2 bits asymmetry control. controls asymmetry of v ol /v oh swing for dqa. 044 16 ccb ccb read-write, 7 bits current control b. controls i ol output current for dqb. asymb read-write, 2 bits asymmetry control. controls asymmetry of v ol /v oh swing for dqb. 045 16 napx napxa read-write, 5 bits nap exit. specifies length of nap exit phase a. napx read-write, 5 bits nap exit. specifies length of nap exit phase a + phase b. dqs read-write, 1 bits dq select. selects cmd framing for nap/pdn exit.
rev.0.9 / dec.2000 31 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary 046 16 pdnxa pdnxa read-write, 13 bits pdn exit. specifies length of pdn exit phase a. 047 16 pdnx pdnx read-write, 13 bits pdn exit. specifies length of pdn exit phase a + phase b. 048 16 tparm tcas read-write, 2 bits t cas-c core parameter. determines t offp datasheet parameter. tcls read-write, 2 bits t cls-c core parameter. determines t cac and t offp parameters. tcdly0 read-write, 3 bits t cdly0-c core parameter. programmable delay for read data. 049 16 tfrm tfrm read-write, 4 bits t frm -c core parameter. determines row -c ol packet framing interval. 04a 16 tcdly1 t cd ly 1 read-write, 3 b its t cd ly 1-c core p arameter. programmable delay for read data. 04c 16 tcycle tcycle read-write, 14 bits t cycle datasheet parameter. specifies cycle time in 64ps units. 048 16 skip as read-only, 1 bits autoskip value established by the setf command. mse read-write, 1 bits manual skip enable. allows the ms value to override the as value. ms read-write, 1 bits manual skip value. 04 d 16- test7 7 test 77 read-write, 16 bit s test register . write with zero after sio reset. 04 e 16- test 78 test 78 read-write, 16 bit s test register. 04 f 16- test 79 test 79 read-write, 16 bit s test register . do not read or write after sio reset. 080 16 - 0ff 1 6 reserved reserved vendor-specific vendor-specific test registers. do not read or write after sio reset. table 15: control register summary sa11..sa 0 registe r fiel d read-write / r ead-only descriptio n
32 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary . . figure 27: init register figure 28: cnfga re gister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control register: init read/write register. reset values are undefined except as affected by sio reset as noted belo w. setr/clrr reset does not affect this register. sdevid 5. .0 - serial device identification. compared to sdev 5. .0 serial address field of serial request packet for register read/write transac- tions. this determines which rdram is selected for the register read or write operation. sdevid resets to 3f 16 . sdevid4..sdevid0 0 srp psx nsr psr lsr 0 psx - power exit select. pdn and nap are exited with (=0) or without (=1) a device address on the dqa5..0 pins. srp - sio repeater. controls value on sio1; sio1=sio0 if srp=1, sio1=1 if srp=0. srp resets to 1. nap self-refresh. nsr=1 enables self-refresh in nap mode. nsr resets to 0. pdn self-refresh. psr=1 enables self-refresh in pdn mode. psr resets to 0. low power self-refresh. lsr=1 enables longer self-refresh interval. the self-refresh supply current is reduced . lsr resets to 0. temperature sensing enable. ten=1 enables temperature sensing circuitry, permitting the tsq bit to be read to determine if a thermal trip point has been exceeded. ten resets to 0. temperature sensing output. tsq=1 when a temperature trip point has been exceeded, tsq=0 when it has not. tsq is available during a current control operation (see figure 52:). rdram disable. dis=1 causes rdram to ignore nap/pdn exit sequence, dis=0 permits normal operation. this mechanism disables an rdram. dis resets to 0. address: 021 16 ten t sq dis sde vid 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control register: cnfga address: 0 23 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read-only register . refbit2..0 - refresh bank bits. specifies the number of high order bank address bits to be ignored during refa and refp commands. permits multi-bank refresh in future rdrams . dbl - doubled-bank. dbl=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. dbl=0 means no dependency. mver5..0 - manufacturer version. specifies the manufac- turer identification number. pv er5..0 - protocol version. specifies the direct protocol version used by this device : 0 - compliant with version 0.62 and eco1-eco18. 1 - compliant with version 0.7 and eco1-eco38. 2 to 63 - reserved refbit2..0 = 101 pver5..0 = 000001 dbl 1 mver5..0 = mmmmmm note : in rdrams with protocol version 1 pver[5:0] = 000001, the range of the pdnx field (pdnx[2:0] in the pdnx register) may not be large enough to specify the location of the restricted interval in figure 47:. in this case, the effective t s4 parameter must increase and no row or column packets may overlap the restricted interval. see figure 47: and table 17:.
rev.0.9 / dec.2000 33 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary .. figure 29: cnfgb register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control register: cnfgb address: 0 24 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read-only register . byt - byte width. b=1 means the device reads and writes 9-bit memory bytes. b=0 means 8 bits. devtyp2..0 - device type. devtyp = 000 means that this device is an rdram . devtyp2..0 = 000 byt b sver5..0 = ssssss corg 4.. 0 = 01000 spt 1 spt - split-core. spt=1 means the core is split, spt=0 means it is not. corg4..0 - core organization. this field specifies the number of bank (5 bits), row (9bits), and column (7 bits) address bits. sver5..0 - stepping version. specifies the mask version number of this device. figure 30: test register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value of test34 is zero (from sio reset) this register are used for testing purposes. it must not be read or written after sio reset except prior to the setr/clrr sequence when it is written with a temporary value. after setr/clrr it is rewritten to 0000 16 . control register: test34 address: 0 22 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 31: devid register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined. device identification register. devid4..devid0 is compared to dr4 .. dr0 , dc4..dc0, and dx4..dx0 fields for all memory read or write transactions . this d etermine s which rdram is selected for the memory read or write transaction . control register: devid address: 040 16 0 devid4..devid0 0 0 0 0 0 0 0 0 0 0
34 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 32: refb register figure 33: cca register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is zero (from setr/clrr). refresh bank register. refb 4. .refb0 is the bank that will be refreshed next during self-refresh. refb 4. .0 is incremented after each self-refresh activate and precharge operation pair. control register: refb address: 041 16 0 0 0 0 0 0 0 0 0 0 0 0 refb 4. .refb0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is zero (setr/clrr or sio reset). cca6..cca0 - current control a. controls the i ol output current for the dqa8..dqa0 pins. asyma0 control the asymmetry of the v ol /v oh voltage swing about the v ref reference voltage for the dqa8..0 pins; control register: cca address: 043 16 0 0 0 0 0 0 0 0 cca6..cca0 1..0 asyma 1..0 asyma0 odf r da 1 0.12 0.81 0 0.00 1.00 where odf is the overdrive factor (the extra i ol current sunk by the rsl output when asyma0 is set) and table18 shows the r da parameter range, where r da = 1/(1+2*odf) figure 34: refr register figure 35: ccb register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is zero (from setr/clrr). refresh row register. refr8..refr0 is the row that will be refreshed next by the refp command or by self-refresh. refr8..0 is incremented when br 4. .0=11 1 11 for the ref a c ommand. refr8..0 is incremented when refb 4. .0=11 1 11 for self-refresh. control register: refr address: 042 16 0 0 0 0 0 0 0 refr8..refr0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is zero (setr/clrr or sio reset). cc b6 ..cc b0 - current control b. controls the i ol output current for the dq b8 ..dq b0 pins. asymb0 control the asymmetry of the v ol /v oh voltage swing about the v ref reference voltage for t he d qb8..0 pins. control register: ccb address: 044 16 0 0 0 0 0 0 0 0 ccb6..ccb0 1..0 asymb 1..0 asymb0 odf r da 1 0.12 0.81 0 0.00 1.00 where odf is the overdrive factor (the extra i ol current sunk by the rsl output when asymb0 is set) and table18 shows the r da parameter range, where r da = 1/(1+2*odf)
rev.0.9 / dec.2000 35 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary . figure 36: napx register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control register: napx address: 045 16 read/write register. reset value is undefined note : t scycle is t cycle1 (sck cycle time) napxa4..0 - nap exit phase a. this field specifies the number of sck cycles during the first phase for exiting nap mode . it must satisfy: napxa?t scycle > t napxa,max do not set this field to zero. 0 0 0 0 0 0 dqs napxa4..0 napx 4 ..0 n apx 4 ..0 - nap exit phase a plus b. this field specifies the number of sck cycles during the first plus second phase s for exiting nap m ode . it must satisfy: napx?t scycle > t napxa,max +t napxb,max do not set this field to zero. dqs - dq select. this field specifies the number of sck cycles (0 => 0.5 cycles, 1 => 1.5 cycles) between the cmd pin framing sequence and the device selection on dq5..0. figure 37: pdnxa register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined pdnxa4..0 - pdn exit phase a. this field specifies the number of (64?sck cycle) units during the first phase for exiting pdn mode. it must satisfy: pdnxa?64?t scycle > t pdnxa,max do not set this field to zero. note - only pdnxa5..0 are implemented. control register: pdnxa address: 046 16 0 0 0 pdnxa12..0 figure 38: pdnx register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined pdnx4..0 - pdn exit phase a plus b. this field spec- ifies the number of (256?sck cycle) units during the first plus second phases for exiting pdn mode. it must satisfy: pdnx?256?t scycle > pdnxa?64?t scycle + t pdnxb,max if this cannot be satisfied, then the maximum pdnx value should be written, and the t s4 /t h4 timing window will be modified (see figure 49:). do not set this field to zero. note - only pdnx2..0 are implemented. control register: pdnx address: 047 16 0 0 0 pdnx 1 2..0
36 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary . figure 39: tparm register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined . tcas1..0 - specifies the t cas -c core parameter in t cycle units. this should be ?10? (2?t cycle ). tcls1..0 - specifies the t cls -c core parameter in t cycle units. should be ?10? (2?t cycle ). t cdly0 - specifies the t cdly0-c c ore parameter in t cycle units. this adds a programmable delay to q (read data) packets, permitting round trip read delay to all devices to be equalized. this field may be written with the values ?010? (2?t cycle ) through ?101? (5?t cycle ). control register: tparm address: 048 16 0 0 0 0 0 0 0 0 0 0 0 0 tcas tcls the equations relating the core parameters to the datasheet parameters follow : t cas -c = 2?t cycle t cls -c = 2?t cycl e t cps -c = 1?t cycle not programmabl e t offp = t cps -c + t cas -c + t cls -c - 1?t cycle = 4? t cycle t rcd = t rcd -c + 1?t cycle - t cls -c = t rcd -c - 1?t cycle t cac = 3?t cycle + t cls-c + t cdly0-c + t cdly1-c (see table below for programming ranges) tcdly0 011 011 101 100 tcdly0 010 010 3?t cycle 3?t cycle 5?t cycle 4?t cycle t cdly0-c 3?t cycle 2?t cycle 010 001 010 010 tcdly1 000 000 2?t cycle 1?t cycle 2?t cycle 2?t cycle t cdly1-c 0?t cycle 0?t cycle 10?t cycle 9?t cycle 12?t cycle 11?t cycle t cac @ t cycle = 3.3ns 8?t cycle 7?t cycle 10?t cycle 9?t cycle 12?t cycle 11?t cycle t cac @ t cycle = 2.5ns 8?t cycle not allowed figure 40: tfrm register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined. tfrm3..0 - specifies the position of the framing point in t cycle units. this value must be greater than or equal to the t frm,min parameter. this is the minimum offset between a row packet (which places a device at attn) and the first col packet (directed to that device) which must be framed. this field may be written with the values ?0111? (7?t cycle ) through ?1010? (10?t cycle ). tfrm is usually set to the value which matches the largest t rcd,min parameter (modulo 4?t cycle ) that is present in an rdram in the memory system. thus, if an rdram with t rcd,min = 11?t cycle were present, then tfrm would be programmed to 7?t cycle . control register: tfrm address: 049 16 0 0 0 0 0 0 0 0 0 0 0 0 tfrm3..0 figure 41: trdly register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined. t cd ly1 - specifies the value of the t cd ly 1-c core p arameter in t cycle u nits. this adds a programmable delay to q (read data) packets, permitting round trip read delay to all devices to be equalized. this field may be written with the values ?0 0 0? (0?t cycle ) through ? 0 10? (2? t cycle ) . refer to figure 39: for more details. control register: t cd ly 1 address: 04a 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tcdly1
rev.0.9 / dec.2000 37 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 43: test register figure 42: skip register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register (except as field) reset value is zero (sio reset). as-autoskip. read-only value determined by auto skip circuit and stored when setf serial command is rdram during initialization. in figure58, as=1 corresponds to the early q(a1) packet and as=0 to the tcycle later for the four uncertain cases. mse- manual skip enable (0=auto, 1=manual). ms-manual skip (ms must be 1 when mse=1). during initializa- tion, the rdrams at the furthest point in the fifth read domain may have selected the as=0 value, placing them at the closest point in a sixth read domain. setting the mse/ms fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain. control register: skip address: 04 b 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 as mse as 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write registers. reset value of test78,79 is zero ( sio reset). do not read or write test78,79 after sio reset. test77 must be written with zero after sio reset. these registers must only be used for testing purposes except prior to the setr/clrr sequence when test78 is written with a temporary value.after setr/clrr it is rewritten to 0000 16 . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 control register: test7 7 address: 04d 16 control register: test78 address: 04e 16 control register: test79 address: 04f 16 figure 44: tcycle register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write register. reset value is undefined tcycle13..0 - specifies the value of the t cycle datasheet parameter in 64ps units. for the t cycle,min of 2.5ns (2500ps), this field should be written with the value ?00027 16 ? (39?64ps). control register: tcycle address: 04c 16 0 0 tcycle13..tcycle0
38 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary power state management table16 summarizes the power states available to a direct rdram. in general, the lowest power states have the longest operational latencies. for example, the relative power levels of pdn state and stby state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. pdn state is the lowest power state available. the informa- tion in the rdram core is usually maintained with self- refresh; an internal timer automatically refreshes all rows of all banks. pdn has a relatively long exit latency because the tclk/rclk block must resynchronize itself to the external clock signal. nap state is another low-power state in which either self- refresh or refa-refresh are used to maintain the core. see ? refresh ? on page42 for a description of the two refresh mechanisms. nap has a shorter exit latency than pdn because the tclk/rclk block maintains its synchroniza- tion state relative to the external clock signal at the time of nap entry. this imposes a limit (t nlimit ) on how long an rdram may remain in nap state before briefly returning to stby or attn to update this synchronization state. figure 45: summarizes the transition conditions needed for moving between the various power states. at initialization, the setr/clrr reset sequence will put the rdram into pdn state. the pdn exit sequence involves an optional pdev specification and bits on the cmd and sio in pins. once the rdram is in stby, it will move to the attn/attnr/attnw states when it receives a non- broadcast rowa packet or non-broadcast rowr packet with the attn command. the rdram returns to stby from these three states when it receives a rlx command. alternatively, it may enter nap or pdn state from attn or stby states with a napr or pdnr command in an rowr packet. the pdn or nap exit sequence involves an optional pdev specification and bits on the cmd and sio0 pins. the rdram returns to the attn or stby state it was originally in when it first entered nap or pdn. an rdram may only remain in nap state for a time t nlimit . it must periodically return to attn or stby. the naprc command causes a napdown operation if the rdram?s ncbit is set. the ncbit is not directly visible. it is undefined on reset. it is set by a nap or naprc command to the rdram, and it is cleared by an act command to the rdram. it permits a controller to manage a set of rdrams in a mixture of power states. stby state is the normal idle state of the rdram. in this state all banks and sense amps have usually been left precharged and rowa and rowr packets on the row pins are being monitored. when a non-broadcast rowa packet or non-broadcast rowr packet (with the attn command) packet addressed to the rdram is seen, the rdram enters attn state (see the right side of figure 46:). this requires a time t sa during which the rdram activates the specified row of the specified bank. a time tfrm?t cycle after the row packet, the rdram will be able to frame col packets (tfrm is a control register field - see figure 40:). once in attn state, the rdram will automatically transition to the attnw and attnr states as it receives wr and rd commands. once the rdram is in attn, attnw, or attnr states, it will remain there until it is explicitly returned to the stby table 16: power state summary power state description blocks consuming power power state description blocks consuming power pdn powerdown state. self-refresh nap nap state. similar to pdn except lower wake-up latency. self-refresh or refa-refresh tclk/rclk-nap stby standby state. ready for row packets. refa-refresh tclk/rclk row demux receiver attn attention state. ready for row and col packets. refa-refresh tclk/rclk row demux receiver col demux receiver attnr attention read state. ready for row and col packets. sending q (read data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq mux transmitter core power attnw attention write state. ready for row and col packets. ready for d (write data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq demux receiver core power
rev.0.9 / dec.2000 39 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary state with a rlx command. a rlx command may be given in an rowr, colc , or colx packet (see the left side of figure 46:). it is usually given after all banks of the rdram have been precharged; if other banks are still activated, then the rlx command would probably not be given. if a broadcast rowa packet or rowr packet (with the attn command) is received, the rdram?s power state doesn?t change. if a broadcast rowr packet with rlxr command is received, the rdram goes to stby. figure 47: shows the nap entry sequence (left). nap state is entered by sending a napr command in a row packet. a time t asn is required to enter nap state (this specification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the napr command. the rdram may be in attn or stby state when the napr command is issued. when nap state is exited, the rdram will return to the original starting state (attn or stby). if it is in attn state and a rlxr command is specified with napr, then the rdram will return to stby state when nap is exited. figure 47: also shows the pdn entry sequence (right). pdn state is entered by sending a pdnr command in a row packet. a time t asp is required to enter pdn state (this spec- ification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the pdnr command. the rdram may be in attn or stby state when the pdnr command is issued. when pdn state is exited, the rdram will return to stby. after a pdn exit, the rdram maybe consume power as if it is in attn state until a rlx command is received.also the curent and slew- rate-control levels must be re-established. the rdram?s write buffer must be retired with the appro- priate cop command before nap or pdn are entered. also, all the rdram?s banks must be precharged before nap or pdn are entered. the exception to this is if nap is entered with the nsr bit of the init register cleared (disabling self- refresh in nap). the commands for relaxing, retiring, and precharging may be given to the rdram as late as the ropa0, copa0, and xopa0 packets in figure 47:. no broadcast packets nor packets directed to the rdram entering nap or pdn may overlay the quiet window. this window extends for a time t npq after the packet with the napr or pdnr command. figure 48: shows the nap and pdn exit sequences. these sequences are virtually identical; the minor differences will be highlighted in the following description. before nap or pdn exit, the ctm/cfm clock must be stable for a time t ce . then, on a falling and rising edge of sck, if there is a ? 01 ? on the cmd input, nap or pdn state will be exited. also, on the falling sck edge the sio0 input must be at a 0 for nap exit and 1 for pdn exit. if the psx bit of the init register is 0, then a device pdev5..0 is specified for nap or pdn exit on the dqa5..0 pins. this value is driven on the rising sck edge 0.5 or 1.5 sck cycles after the original falling edge, depending upon the value of the dqs bit of the napx register. if the psx bit of the init register is 1, then the rdram ignores the pdev5..0 address packet and exits nap or pdn when the wake-up sequence is presented on the cmd wire. the row and col pins must be quiet at a time t s4 /t h4 around the indi- cated falling sck edge (timed with the pdnx or napx register fields). after that, row and col packets may be directed to the rdram which is now in attn or stby state. figure 45: pow er state transition diagram automatic automatic a u t o m a t i c a u t o m a t i c a u t o m a t i c a u t o m a t i c attnr attnw attn stb y setr /clrr napr notation: setr /clrr - setr /clrr reset sequence i n srq packet s t nlimit nap napr ? rlxr pdev.cmd? si o0 pdnr pdn pdnr pdev.cmd?si o0 n a p r p d n r a t t n r l x pdnr - pdnr command in rowr packet napr - napr command in rowr packet rlxr - rlx command in rowr packet rlx - rlx command in rowr,colc,colx packets sio0 - sio0 input value pdev.cmd - (pdev=devid)?(cmd=01) attn - rowa packet (non-broadcast) or rowr packet ( non-broadcast) with attn command
40 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 49: shows the constraints for entering and exiting nap and pdn states. on the left side, an rdram exits nap state at the end of cycle t 3 . this rdram may not re- enter nap state for an interval of t nu0 . the rdram enters nap state at the end of cycle t 12 . this rdram may not re- exit nap state for an interval of t nu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. napx is the value in the napx field in the napx register. on the right side of figure 48:, an rdram exits pdn state at the end of cycle t 3 . this rdram may not re-enter pdn state for an interval of t pu0 . the rdram enters pdn state at the end of cycle t 13 . this rdram may not re-exit pdn state for an interval of t pu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. pdnx is the value in the pdnx field in the pdnx register. figure 46: stby entry ( left) and stby exit ( right) figure 47: nap entry ( left) and pdn entry ( right) stby attn ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 t as rlxr power state attn power state stby t sa rop a0 rlxc rlxx tfrm? t cycle rop = non-broadcast rowa or rowr/attn a0 = {d0,b0,r0} a1 = {d1,b1,c1} no col packets may be placed in the three indicated positions; i.e. at (tfrm - {1,2,3})?t cycle . a col packet to device d0 (or any other device) is okay at (tfrm)?t cycle or later. a col packet to another device (d1!= d0) is okay at (tfrm - 4)?t cycle or earlier. cop a1 xop a1 cop a1 xop a1 cop a1 xop a1 cop a0 xop a0 cop a1 xop a1 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 rop a0 ( napr) power state power state a th e (eventual) nap/pdn exit will be to the same attn/ stby state the rdram was in prior to nap/pdn entry t cd rop a1 cop a0 xop a0 cop a1 xop a1 t asn attn/stby a nap rop a0 ( pdnr) rop a1 cop a0 xop a0 cop a1 xop a1 t asp attn/stby a pdn quiet quiet quiet quiet t cd t npq t npq restricted restricted restricted restricted a0 = {d0,b0,r0,c0} a1 = {d1,b1,r1,c1} no row or col packets directed to device d0 may overlap the restricted interval. no broadcast row packets may overlap the quiet interval. row or col packets to a device other than d0 may overlap the restricted interval. row or col packets directed to device d0 after the restricted interval will be ignored.
rev.0.9 / dec.2000 41 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 48: nap and pdn exit figure 49: nap entry/exit windows (left) and pdn entry/e xit windows (right) ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rop dqs=0 b,c sck cmd si o0 si o1 01 0/1 a 0/1 a pdev5..0 b pdev5..0 b dqs=1 b t s3 t s3 t h3 t h3 t ce a use 0 for nap exit, 1 for pdn exit b device selection timing slot is selected by dqs field of napx register the p acket is repeated from s i o0 t o s i o1 restricted power state dqs=0 d dqs=1 d c the dos field must be written with ?1? for this rdram d the psx field determines the start of nap / pdn exit. t s4 t h4 stby nap/pdn ( napx)?t scycle )/( 256?pdnx?t scycle ) restricted t s4 t h4 cop xop no row packets may overlap the restricted interval no col packets may overlap the restricted interval if device pdev is exiting the nap-a or pdn-a states rop cop xop if psx = 1 in init register, then nap / pdn exit is broadcast (no pdev field) effective hold becomes t h4 ?=t h4 + [pdnxa *64* t scycle + t pdnxb,max ]-[pdnx*256*t scycle] if [pdnx*256*t scycle ] < [pdnxa *64* t scycle + t pdnxb,max ] ctm/cfm cmd sck row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 22 t 19 t 23 napr ctm/cfm cmd sck row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 17 t 21 t 18 t 19 01 01 t nu0 t nu0 = 5?t cycle + (2+napx)?t scycle no entry t nu1 = 8?t cycle - (0.5?t scycle ) pdnr 01 01 no exit t nu1 t pu0 no entry no exit t pu1 = 23?t cycle if nsr=1 if nsr=0 t pu0 = 5?t cycle + (2+256?pdnx)?t scycle t pu1 = 8?t cycle - (0.5?t scycle ) = 23?t cycle if psr=1 if psr=0 nap entry nap exit pdn entry pdn exit
42 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary refresh rdrams, like any other dram technology, use volatile storage cells which must be periodically refreshed. this is accomplished with the refa command. figure 50: shows an example of this. the refa command in the transaction is typically a broad- cast command (dr4t and dr4f are both set in the rowr packet), so that in all devices bank number ba is activated with row number refr, where refr is a control register in the rdram. when the command is broadcast and attn is set, the power state of the rdrams (attn or stby) will remain unchanged. the controller increments the bank address ba for the next refa command. when ba is equal to its maximum value, the rdram automatically incre- ments refr for the next refa command. on average, these refa commands are sent once every t ref /2 bbit+rbit (where bbit are the number of bank address bits and rbit are the number of row address bits) so that each row of each bank is refreshed once every t ref interval. the refa command is equivalent to an act command, in terms of the way that it interacts with other packets (see table9). in the example, an act command is sent after t rr to address b0, a different (non-adjacent) bank than the refa command. a second act command can be sent after a time t rc to address c0, the same bank (or an adjacent bank) as the refa command. note that a broadcast refp command is issued a time t ras after the initial refa command in order to precharge the refreshed bank in all rdrams. after a bank is given a refa command, no other core operations (activate or precharge) should be issued to it until it receives a refp. it is also possible to interleave refresh transactions (not shown). in the figure, the act b0 command would be replaced by a refa b0 command. the b0 address would be broadcast to all devices, and would be {broad- cast,ba+2,refr}. note that the bank address should skip by two to avoid adjacent bank interference. a possible bank incrementing pattern would be: { 12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29, 27, 24, 22, 17, 31 }. every time bank 31 is reached , the refa command would automatically increment the refr register. a second refresh mechanism is available for use in pdn and nap power states. this mechanism is called self-refresh mode. when the pdn power state is entered, or when nap power state is entered with the nsr control register bit set, then self-refresh is automatically started for the rdram. self-refresh uses an internal time base reference in the rdram. this causes an activate and precharge to be carried out once in every t ref /2 bbit+rbit interval. the refb and refr control registers are used to keep track of the bank and row being refreshed. before a controller places an rdram into self-refresh mode, it should perform refa/refp refreshes until the bank address is equal to the last value. (this will be 31 for all sequences) this ensures that no rows are skipped. likewise, when a controller returns an rdram to refa/refp refresh, it should start with the minimum bank address value ( 12 for the example sequence ) note that for this rdram, the upper bank address bit is not used. this bit should be set to ?0? in all bank address fields, but with one exception. when refa and refp commands are specified in rowr packets, it will be necessary to set the upper bank bit to values other than :0? when other rdrams with no more banks are present on the channel. figure51 illustrates the requirement imposed by the t burst . parameter. after pdn or nap (when self-refresh is enabled) power states are exited, the controller must refresh all banks of the rdram once during the interval t burst after the restricted interval on the row and col buses. this will ensure that regardless of the state of self-refresh during pdn or nap, the t ref,max parameter is met for all banks. during the t burst interval, the banks may be refreshed in a single burst, or they may be scattered throughout the interval. note that the first and last banks to be refreshed in the t burst interval are numbers 12 and 31, in order to match the example refresh sequence.
rev.0.9 / dec.2000 43 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 50: refa/refp refresh transaction example ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 ref a a0 act c0 t ras t rc t rp transaction a: refa a0 = {broadcast,ba,refr} a1 = {broadcast,ba} transaction c: xx c0 = {dc, ==ba, rc} ref a d0 t ref /2 bbit+rbit bbit = # bank address bits rbit = # row address bits act b0 transaction d: refa d0 = {broadcast,ba+1,refr} refb = refb3..refb0 refr = refr8..refr0 t rr transaction b: xx b0 = {db, /= { ba ,ba+1,ba-1} , rb} refp a 1 ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 rop dqs=0 b,c sck cmd si o0 si o1 01 0/1 a 0/1 a dqs=1 b t ce a use 0 for nap exit, 1 for pdn exit the p acket is repeated from s i o0 t o s i o1 restricted power state dqs=0 dqs=1 t s4 t h4 stby nap/pdn ( napx)?t scycle )/( 256?pdnx?t scycle ) restricted t s4 t h4 cop xop rop cop xop refa b12 refa b31 t burst 32 bank refresh sequence figure 51: nap/pdn exit -t burst requirement
44 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rev. 0.9 / dec.2000 current and temperature control figure 52: shows an example of a transaction which performs current control calibration. it is necessary to perform this operation once to every rdram in every t cctrl interval in order to keep the i ol output current in its proper range. this example uses four colx packets with a cal command. these cause the rdram to drive four calibration packets q(a0) a time t cac later. an offset of t rdtocc must be placed between the q(a0) packet and read data q(a1)from the same device. these calibration packets are driven on the dqa4..3 and dqb4..3 wires. the tsq bit of the init register is driven on the dqa5 wire during same interval as the calibration packets. the remaining dqa and dqb wires are not used during these calibration packets. the last colx packet also contains a sam command (concatenated with the cal command). the rdram samples the last calibra- tion packet and adjusts its i ol current value. unlike ref commands, cal and sam commands cannot be broadcast. this is because the calibration packets from different devices would interfere. therefore, a current control transaction must be sent every t cctrl /n, where n is the number of rdrams on the channel. the device field da of the address a0 in the cal/sam command should be incremented after each transactions. figure53 shows an example of a temperature calibration sequence to the rdram. this sequence is broadcast once every t temp interval to all the rdrams on the channel. the tcen and tcal are rop commands, and cause the slew rate of the output drivers to adjust for temperature drift. during the quiet interval t tcquiet the devices being cali- brated can?t be read, but they can be written. figure 52: current control cal/sam transaction example ctm/cfm dqa8..0 dqb8..0 col4 .. col0 row2 .. row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 transaction a 0: cal/sam a0 = {da, bx} transaction a1: rd a1 = {da, bx} cal a 0 cal a2 q (a0) t cac cal a 0 cal a 0 cal/s am a0 cal dqa5 of the first calibrate packet has the inverted tsq bit q (a 1) t readtocc a2 = {da+1, bx} transaction a 2 : cal/sam read data from the same device from an earlier rd command must be at this packet position or earlier. read data from a different device from an earlier rd command can be anywhere prior to the q(a0) packet. . q (a 1) t ccsamtoread read data from a different device from a later rd command can be anywhere after to the q(a0) packet. read data from the same device from a later rd command must be at this packet position or later. t cctrl of init control register; i.e. logic 0 or high voltage means hot temp. when used for monitoring, it should be enabled with the the dqa3bit ()current control one value) in case there is no rdram present; hottemp = dqa5 * dqa3 note that dqb3 could be used instead of dqa3
rev.0.9 / dec.2000 45 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 53: temperature calibration (tcen-tcal) transactions to rdram ctm/cfm dqa8.0 dqb8..0 col4 ..col0 row2 ..row0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 t 16 t 20 t 24 t 28 t 17 t 21 t 25 t 29 t 18 t 22 t 26 t 30 t 19 t 23 t 27 t 31 t 32 t 36 t 40 t 44 t 33 t 37 t 41 t 45 t 34 t 38 t 42 t 46 t 35 t 39 t 43 t 47 any row packet may be placed in the gap between the row packets with the tcen and tcal commands t tcen tcen tcal tcen t tcal no read data from devices t tcquiet being calibrated t temp
46 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary electrical conditions . a vcmos must remain on as long as vdd is applied and cannot be turned off. b.vdih is typically equal to vterm(1.8v+/- 0.1v) under dc conditions in a system. c. voltage undershoot is limited to -0.7v for a duration of less than 5ns. d. voltage overshoot is limited to vcmos + 0.7v for a duration of less than 5ns. table 17: electrical conditions symbol parameter and conditions min max unit t j junction temperature under bias - 100 c v dd, v dda supply voltage 2.50 - 0.13 2.50 + 0.13 v v dd ,n , v dda ,n supply voltage droop (dc) d uring nap interval ( t nlimit ) - 2. 0 % v d d ,n , v d da ,n supply voltage ripple (ac) during nap interval ( t nlimit ) - 2.0 2. 0 % v cmos supply voltage for cmos pins (2.5v controllers) v dd v dd v supply voltage for cmos pins (1.8v controllers) 1.80 - 0 .1 1.80 + 0 .2 v v ref reference voltage 1.40 - 0.2 1.40 + 0.2 v v dil rsl data input - low voltage v ref - 0.5 v ref - 0. 2 v v dih rsl data input - high voltage v ref + 0.2 v ref + 0.5 v r da rsl data asymmetry: r da = (v dih - v ref ) / ( v ref - v dil ) 0.67 1.0 - v cm rsl clock input - common mode v cm = (v cih - v cil )/2 1.3 1.8 v v cis,ctm rsl clock input swing: v cis = v cih - v cil (ctm,ctmn pins). 0 .35 1.0 v v cis ,cfm rsl clock input swing: v cis = v cih - v cil (cfm,cfmn pins). 0. 225 1.0 v v il,cmos cmos input low voltage - 0.3 c v cmos /2 - 0.25 v v ih,cmos cmos input high voltage v cmos /2 + 0.25 v cmos +0.3 d v
rev.0.9 / dec.2000 47 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary timing conditions. table 18: timing conditions symbol parameter min max unit figure(s) t dcw domain crossing window -0.1 0.1 t cycle figure 60: t dr , t df dqa/dqb/row/col input rise/fall times (20% to 80%) use the minimum value of these parameters during testing. 0.2 0.65 ns figure 55: t s , t h dqa/dqb/row/col-to-cfm setup/hold @ t cycle =2.50ns/2.81ns/3.33ns 0.200 b /0.240 b,c /0.275 b,d - ns figure 55: t dr1, t df1 sio0, sio1 input rise and fall times - 5.0 ns figure 57: t dr2, t df2 cmd, sck input rise and fall times - 2.0 ns figure 57: t cycle1 sck cycle time - serial control register transactions 1000 - ns figure 57: sck cycle time - power transitions 10 - ns figure 57: t s1 cmd setup time to sck rising or falling edge e 1.25 - ns figure 57: t h1 cmd hold time to sck rising or falling edge e 1 - ns figure 57: t ch1 , t cl1 sck high and low times 4.25 - ns figure 57: t s2 sio0 setup time to sck falling edge 40 - ns figure 57: t h2 sio0 hold time to sck falling edge 40 - ns figure 57: t s3 pdev setup time on dqa5..0 to sck rising edge. 0 - ns figure 48:, figure 57: t h3 pdev hold time on dqa5..0 to sck rising edge. 5.5 - ns t s4 row2..0, col4..0 setup time for quiet window -1 - t cycle figure 48: t cycle ctm and cfm cycle times (-600) 3.33 3.83 ns figure 54: ctm and cfm cycle times (-711) 2.80 3.83 ns figure 54: ctm and cfm cycle times (-800) 2.50 3.83 ns figure 54: t cr , t cf ctm and cfm input rise and fall times 0.2 0.5 ns figure 54: t ch , t cl ctm and cfm high and low times 40% 60% t cycle figure 54: t tr ctm-cfm differential (mse/ms=0/0) ctm-cfm differential (mse/ms=1/1) a 0.0 0.9 1.0 1.0 t cycle figure 42: figure 54: t h4 row2..0, col4..0 hold time for quiet window f 5 - t cycle figure 48: t npq quiet on row/col bits during nap/pdn entry 4 - t cycle figure 47: t readtocc offset between read data and cc packets (same device) 12 - t cycle figure 52: t ccsamtoread offset between cc packet and read data (same device) 8 - t cycle figure 52: t ce ctm/cfm stable before nap/pdn exit 2 - t cycle figure 48: t cd ctm/cfm stable after nap/pdn entry 100 - t cycle figure 47: t frm row packet to col packet attn framing delay 7 - t cycle figure 46:
48 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary a. mse/ms are fields of the skip register. for this combination (skip override) the tdcw parameter range is effectively 0.0 to 0 .0 b.t s,min and t h,min for other t cycle values can be interpolated from the timings at the 3 specified t cycle values. c. this parameter also applies to a -800 part when opreated with t cycle =2.81ns. d. this parameter also applies to a -800 or -711part when opreated with t cycle =3.33ns. e. with v il,cmos =0.5v cmos - 0.4v and v ih,cmos = 0.5v cmos + 0.4v f. effective hold becomes th4 = th4 + [pdnxa * 64 * t scycle + t pdnxb,max ] - [pdnx * 256 * t scycle ] if [pdnx * 256 * t scycle ] < [pdnxa * 64 * t scycle + t pdnxb,max ]. see figure 48: t ref refresh interval 32 ms figure 50: t burst interval after pdn or nap (with self-refresh) exit in which all banks of the rdram must be refreshed at least one. 200 m s figure 51: t cctrl current control interval 34t cycle 100ms t cycle/ ms figure 52: t temp temperature control interval 100 ms figure 53: t tcen tce command to tcal command 150 - t cycle figure 53: t tcal tcal command to quiet window 2 2 t cycle figure 53: t tcquiet quiet window (no read data) 140 - t cycle figure 53: t pause rdram delay (no rsl operations allowed) 200.0 m s page28 table 18: timing conditions symbol parameter min max unit figure(s)
rev.0.9 / dec.2000 49 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary timing characteristics table 19: timing characteristics symbol parameter min m ax unit figure(s) t q ctm-to-dqa/dqb output time @ t cycle =2.5ns @ t cycle =2.8ns @ t cycle =3.3ns -0.26 a -0.30 a,b -0.35 a,c +0.26 a +0.30 a,b +0.35 a,c ns figure 56: t qr , t qf dqa/dqb output rise and fall times 0.2 0.45 ns figure 56: t q1 sck-to-sio0 delay @ c load,max = 20pf (sd read data valid) . - 10 ns figure 59: t q1 sck-to-sio0 delay @ c load,max = 20pf (sd read hold ) . 2 - ns figure 59: t qr1 , t qf1 sio out rise/fall @ c load,max = 20pf - 5 ns figure 59: t prop1 sio0-to-sio1 or sio1-to-sio0 delay @ c load,max = 20pf - 10 ns figure 59: t n a p x a nap exit delay - phase a - 50 ns figure 48: t n apx b nap exit delay - phase b - 40 ns figure 48: t p d n x a pdn exit delay - phase a - 4 m s figure 48: t p d n xb pdn exit delay - phase b - 9000 t cycle figure 48: t as attn-to-stby power state delay - 1 t cycle figure 46: t sa stby-to-attn power state delay - 0 t cycle figure 46: t asn attn/stby-to-nap power state delay - 8 t cycle figure 47: t asp attn/stby-to-pdn power state delay - 8 t cycle figure 47: a.t q,min and t q,max for other t cycle values can be interpolated between or extrapolated from the timings at the 3 specified t cycle values. b. this parameter also applies to a -800 part when opreated with t cycle =2.81ns. c. this parameter also applies to a -800 or -711part when opreated with t cycle =3.33ns.
50 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary electrical characteristics table 20: electrical characteristics symbol parameter and conditions min max unit q jc junction-to-case thermal resistance tbd c/watt i ref v ref current @ v ref,max -10 10 m a i oh rsl output high current @ (0 v out v dd ) -10 10 m a i all rsl i ol current @ v o l = 0.9v, v dd,min , t j,max a 3 0.0 90. 0 ma d i ol rsl i ol current resolution step - 2.0 ma r out dynamic output impedance 1 50 - w i ol,nom rsl i ol current @ vol = 1.0v b,c 26.6 30.6 ma i ol_a01,nom rsl i ol current @ vol = 0.9v b,d 30.1 34.1 ma i i,cmos cmos input leakage current @ (0 v i,cmos v cmos ) -10.0 10.0 m a v ol,cmos cmos output voltage @ i ol,cmos = 1.0ma - 0.3 v v oh,cmos cmos output high voltage @ i oh,cmos = -0.25ma v cmos -0.3 - v a. this measurement is made in manual current control mode; i.e. with all output device legs sinking current. b. this measurement is made in automatic current control mode after at least 64 current control calibration operations to a devi ce and after cca and ccb are initialized to a value of 64. this value applies to all dqa and dqb pins. c. this measurement is made in automatic current control mode in a 25 w test system with v term = 1.714v and v ref = 1.375v and with the asyma and asymb register fields set to 0. d. . this measurement is made in automatic current control mode in a 25 w test system with v term = 1.714v and v ref = 1.375v and with the asyma and asymb register fields set to 1.
rev.0.9 / dec.2000 51 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rsl - clocking figure 54: is a timing diagram which shows the detailed requirements for the rsl clock signals on the channel. the ctm and ctmn are differential clock inputs used for transmitting information on the dqa and dqb, outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling ctm edge to the falling ctm edge. the t cl and t ch param- eters are measured from falling to rising and rising to falling edges of ctm. the t cr and t cf rise- and fall-time parame- ters are measured at the 20% and 80% points. the cfm and cfmn are differential clock outputs used for receiving information on the dqa, dqb, row and col outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling cfm edge to the falling cfm edge. the t cl and t ch parameters are measured from falling to rising and rising to falling edges of cfm. the t cr and t cf rise- and fall-time parameters are measured at the 20% and 80% points. the t tr parameter specifies the phase difference that may be tolerated with respect to the ctm and cfm differential clock inputs (the ctm pair is always earlier). figure 54: rsl timing - clock signals v cih 50% v cil 80% 20% ctm ctmn v c i h 50% v c i l 80% 20% cfm cfmn t tr t cf t cf t cr t cr t cycle t cl t ch t cf t cf t cr t cr t cycle t cl t ch
52 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rsl - receive timing figure 55: is a timing diagram which shows the detailed requirements for the rsl input signals on the channel. the dqa, dqb, row, and col signals are inputs which receive information transmitted by a direct rac on the channel. each signal is sampled twice per t cycle interval. the set/hold window of the sample points is t s /t h. the sample points are centered at the 0% and 50% points of a cycle, measured relative to the crossing points of the falling cfm clock edge. the set and hold parameters are measured at the v ref voltage point of the input transition. the t dr and t df rise- and fall-time parameters are measured at the 20% and 80% points of the input transition. figure 55: rsl timing - data signals for receive v dih v ref v dil 80% 20% v cih 50% v cil 80% 20% c fm c fm n dqa t s row dqb t df t dr t h t s t h 0.5?t cycle even odd col
rev.0.9 / dec.2000 53 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary rsl - transmit timing figure 56: is a timing diagram which shows the detailed requirements for the rsl output signals on the channel. the dqa and dqb signals are outputs to transmit informa- tion that is received by a direct rac on the channel. each signal is driven twice per t cycle interval. the beginning and end of the even transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle. the beginning and end of the odd transmit window is at the 25% point and at the 75% point of the current cycle. these transmit points are measured relative to the crossing points of the falling ctm clock edge. the size of the actual transmit window is less than the ideal t cycle /2, as indicated by the non-zero values of t q,min and t q,max . the t q param- eters are measured at the v ref voltage point of the output transition. the t qr and t qf rise- and fall-time parameters are measured at the 20% and 80% points of the output transition. figure 56: rsl timing - data signals for transmit t q,min t q,max t q,max t q,min 0.25?t cycle v qh v ref v ql 80% 20% v cih 50% v cil 80% 20% c tm c tm n t qf t qr even odd 0.75?t cycle 0.75?t cycle dqa dqb
54 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary cmos - receive timing figure 57: is a timing diagram which shows the detailed requirements for the cmos input signals . the cmd and sio0 signals are inputs which receive infor- mation transmitted by a controller (or by another rdram?s sio1 output. sck is the cmos clock signal driven by the controller. all signals are high true. the cycle time, high phase time, and low phase time of the sck clock are t cycle1 , t ch1 and t cl1 , all measured at the 50% level. the rise and fall times of sck, cmd, and sio0 are t dr1 and t df1 , measured at the 20% and 80% levels. the cmd signal is sampled twice per t cycle1 interval, on the rising edge (odd data) and the falling edge (even data). the set/hold window of the sample points is t s1 /t h1. the sck and cmd timing points are measured at the 50% level. the sio0 signal is sampled once per t cycle1 interval on the falling edge. the set/hold window of the sample points is t s2 /t h2. the sck and sio0 timing points are measured at the 50% level. figure 57: cmos timing - data signals for receive v i h ,cmos 50% v il,cmos 80% 20% sck t s 1 cmd t dr 2 t h 1 t s 1 t h 1 even odd t d f2 v i h ,cmos 50% v il,cmos 80% 20% t dr 2 t d f2 t ch1 t cl1 t cycle1 t s 2 sio0 t dr 1 t h 2 t d f1 v i h ,cmos 50% v il,cmos 80% 20%
rev.0.9 / dec.2000 55 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary the sck clock is also used for sampling data on rsl inputs in one situation. figure 48: shows the pdn and nap exit sequences. if the psx field of the init register is zero (see figure 27:), then the pdn and nap exit sequences are broadcast; i.e. all rdrams that are in pdn or nap will perform the exit sequence. if the psx field of the init register is one, then the pdn and nap exit sequences are directed; i.e. only one rdram that is in pdn or nap will perform the exit sequence. the address of that rdram is specified on the dqa[5:0] bus in the set hold window t s3 /t h3 arouond the rising edge of sck. this is shown in figure 58:. the sck timing point is measured at the 50% level, and the dqa[5:0] bus signals are measured at the v ref level. figure 58: cmos timing - device address for nap or pdn exit v i h ,cmos 50% v il,cmos 80% 20% sck v dih v ref v dil 80% 20% dqa[5:0] t s 3 t h 3 pdev
56 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary cmos - transmit timing figure 59: is a timing diagram which shows the detailed requirements for the cmos output signals. the sio0 signal is driven once per t cycle1 interval on the falling edge. the clock-to-output window is t q1,min /t q1,max. the sck and sio0 timing points are measured at the 50% level. the rise and fall times of sio0 are t qr1 and t qf1 , measured at the 20% and 80% levels. figure 59: cmos timing - data signals for transmit v i h ,cmos 50% v il,cmos 80% 20% sck sio0 t qr1 t qf1 v oh,cmos 50% v ol,cmos 80% 20% t q1,max v i h ,cmos 50% v il,cmos 80% 20% t q1,min v oh,cmos 50% v ol,cmos 80% 20% sio0 t dr1 t df1 t qr1 t qf1 t prop1,max t prop1,min or sio1 sio1 or sio0
rev.0.9 / dec.2000 57 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary figure 59: also shows the combinational path connecting sio0 to sio1 and the path connecting sio1 to sio0 (read data only). the t prop1 parameter specified this propagation delay. the rise and fall times of sio0 and sio1 inputs must be t dr1 and t df1 , measured at the 20% and 80% levels. the rise and fall times of sio0 and sio1 outputs are t qr1 and t qf1 , measured at the 20% and 80% levels. rsl - domain crossing window when read data is returned by the rdram, imformation must cross from the receive clock domain (cfm) to the transmit clock domain (ctm). the t tr parameter permits the cfm to ctm phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. a second parameter t dcw is needed in order to describe how the delay between a rd command packet and read data packet varies as a function of the t tr value. figure 60: shows this timing for five distinct values of t tr . case a (t tr =0) is what has been used throughout this docu- ment. the delay between the rd command and read data is t cac . as t tr varies from zero to t cycle (cases a through e), the command to data delay is (t cac -t tr ). when the t tr value is in the range 0 to t dcw,max , the command to data delay can also be (t cac -t tr -t cycle ). this is shown as cases a? and b? (the gray packets). similarly, when the t tr value is in the range (t cycle +t dcw,min ) to t cycle , the command to data delay can also be (t cac -t tr +t cycle ). this is shown as cases d? and e? (the gray packets). the rdram will work reliably with either the white or gray packet timing. the delay value is selected at initialization, and remains fixed thereafter. figure 60: rsl transmit - crossing read domains c fm col t tr ctm dqa/b dqa/b t tr =0 t cycle case a t tr =0 case a? t tr ctm dqa/b dqa/b t tr =t dcw,max case b t tr =t dcw,max case b? t tr ctm dqa/b t tr =0.5?t cycle case c ctm dqa/b dqa/b t tr =t cycle +t dcw,min case d t tr =t cycle +t dcw,min case d? ctm dqa/b dqa/b t tr =t cycle case e t tr =t cycle case e? t tr t tr rd a1 q(a1) q(a1) q(a1) q(a1) t cac -t tr t cac -t tr -t cycle q(a1) q(a1) q(a1) q(a1) q(a1) t cac -t tr t cac -t tr +t cycle t cac -t tr t cac -t tr +t cycle t cac -t tr t cac -t tr -t cycle t cac -t tr ??? ??? ??? ??? ??? ???
58 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary timing parameters table 21: timing parameter summary parameter description min -40 -800 min -45 -800 min -45 -711 min -53 -600 max units figure(s) t rc row cycle time of rdram banks -the interval between rowa packets with act commands to the same bank. 28 28 28 28 - t cycle figure 15: figure 16: t ras ras-asserted time of rdram bank - the interval between rowa packet with act command and next rowr packet with prer a command to the same bank. 20 20 20 20 64 m s b t cycle figure 15: figure 16: t rp row precharge time of rdram banks - the interval between rowr packet with prer a command and next rowa packet with act command to the same bank. 8 8 8 8 - t cycle figure 15: figure 16: t pp precharge-to-precharge time of rdram device - the interval between suc- cessive rowr packets with prer a commands to any banks of the same device. 8 8 8 8 - t cycle figure 12: t rr ras-to-ras time of rdram device - the interval between successive rowa packets with act commands to any banks of the same device. 8 8 8 8 - t cycle figure 13: t rcd ras-to-cas delay - the interval from rowa packet with act command to colc packet with rd or wr command). note - the ras-to-cas delay seen by the rdram core (t rcd-c ) is equal to t rcd-c = 1 + t rcd because of differences in the row and column paths through the rdram interface. 7 9 7 7 - t cycle figure 15: figure 16: t cac cas access delay - the interval from rd command to q read data. the equation for t cac is given in the tparm register in figure 39:. 8 8 8 8 12 t cycle figure 4: figure 39: t cwd cas write delay (interval from wr command to d write data. 6 6 6 6 6 t cycle figure 4: t cc cas-to-cas time of rdram bank - the interval between successive colc commands). 4 4 4 4 - t cycle figure 15: figure 16: t packet length of rowa, rowr, colc, colm or colx packet. 4 4 4 4 4 t cycle figure 3: t rtr interval from colc packet with wr command to colc packet which causes retire, and to colm packet with bytemask. 8 8 8 8 - t cycle figure 17: t offp the interval (offset) from colc packet with rda command, or from colc packet with retire command (after wra automatic precharge), or from colx packet with prex command to the equivalent rowr packet with prer.the equation for t offp is given in the tparm register in figure 39:. 4 4 4 4 4 t cycle figure 14: figure 39: t rdp interval from last colc packet with rd command to rowr packet with prer. 4 4 4 4 - t cycle figure 15: t rtp interval from last colc packet with automatic retire command to rowr packet with prer. 4 4 4 4 - t cycle figure 16: a. or equivalent prec or prex command. see figure 14:. b. this is a constraint imposed by the core, and is therefore in units of m s rather than t cycle .
rev.0.9 / dec.2000 59 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary absolute maximum ratings i dd - current profile table 22: absolute maximum ratings symbol parameter min max unit v i,abs voltage applied to any rsl or cmos pin with respect to gnd - 0.3 v dd +0.3 v v dd,abs , v dda,abs voltage on vdd and vdda with respect to gnd - 0.5 v dd +1.0 v t store storage temperature - 50 100 c table 23: current profile a i dd value rdram power state and steady-state transaction rates b min max@ t cycle =3.33ns max@ t cycle =2.81ns max@ t cycle =2.50ns unit i dd,pdn device in pdn, self-refresh enabled and init.lsr=0 - 6000 6000 6000 m a i dd,nap device in nap. - 4.2 4.2 4.2 ma i dd,stby device in stby. this is the average for a device in stby with (1) no packets on the channel, and (2) with packets sent to other devices. - 110 120 130 ma i dd,refresh device in stby, and refreshing rows at the t ref,max period. - 120 130 140 ma i dd,attn device in attn. this is the average for a device in attn with (1) no packets on the channel, and (2) with packets sent to other devices. 180 190 200 ma i dd,attn-w device in attn. act command every 8*t cycle , pre command every 8*t cycle , wr command every 4 * tcycle, and data is 1100..1100 - 600 700 750 ma i dd,attn-r device in attn. act command every 8*t cycle , pre command every 8*t cycle , rd command every 4 * tcycle, and data is 1111..1111 c - 550 650 700 ma a. the numbers in this table are not fixed yet. b. cmos interface consumes no power in all power states. c. this does not include tje i ol sink current. the rdram dissipates i ol * v ol in each output driver when a logic one is driven. table 24: supply current at initialization a symbol parameter allowed range of tcycle vdd min max unit i dd,pwrup,d i dd from power-on to setr 3.33ns to 3.83ns 2.50ns to 3.32ns v dd,min - 20 b 26 a ma i dd,setr,d i dd from setr to clrr 3.33ns to 3.83ns 2.50ns to 3.32ns v dd,min - 250 a 332 a ma a. the numbers in this table are specifications. b. the supply current will be 150ma when t cycle is in the range 15ns to 1000ns.
60 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary table 25: rsl pin parasitics symbol parameter and conditions - rsl pins min max unit l i rsl effective input inductance 4.0 nh l 12 mutual inductance between any dqa or dqb rsl signals. 0.2 nh mutual inductance between any row or col rsl signals. 0.6 nh d l i difference in l i value between any rsl pins of a single device. - 1.8 nh c i rsl effective input capacitance a (800) rsl effective input capacitance a (711) rsl effective input capacitance a (600) 2.0 2.0 2.0 2.4 2.4 2.6 pf pf pf c 12 mutual capacitance between any rsl signals. - 0.1 pf d c i difference in c i value between average of {ctm, ctmn, cfm, cfmn} and any rsl pins of a single device. - 0.06 pf r i rsl effective input resistance 4 15 w a. this value is a combination of the device io circuitry and package capacitances measureed at vdd=2.5v and f=400mhz with pin b ased at 1.4v. table 26: cmos pin parasi tics symbol parameter and conditions - rsl pins min max unit l i,cmos cmos effective input inductance 8.0 nh c i,cmos cmos effective input capacitance (sck, cmd) a 1.7 2.1 pf c i,cmos,sio cmos effective input capacitance (sck, cmd) a 7.0 pf a. this value is a combination of the device io circuitry and package capacitances.
rev.0.95 / aug.01 61 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary center-bonded ubga package figure 61: shows the form and dimensions of the recom- mended package for the center-bonded csp device class. figure 61: center-bonded ubga package table27 lists the numerical values corresponding to dimen- sions shown in figure 61:. table 27: center-bonded ubga package dimensions t s a b c d e f g h j 3 4 5 6 7 8 9 e a d e1 10 e2 top bottom 1 2 k l n p r m u e e1 symbol parameter min max unit e1 ball pitch (x-axis) 0.8 0.8 mm e2 ball pitch (y-axis) 0.8 0.8 mm a package body length:256m d-rd 10.56 11.16 mm 288m d-rd 10.96 11.16 mm d package body width:256m d-rd 16.56 16.76 mm 288m d-rd 16.56 16.76 mm e package total thickness 0.65 1.20 mm e1 ball height 0.20 0.43 mm d ball diameter 0.30 0.50 mm
62 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary glossary of terms act activate command from av field. activate to access a row and place in sense amp. adjacent two rdram banks which share sense amps (also called doubled banks). asym cca register field for rsl v ol /v oh . attn power state - ready for row/col packets. attnr power state - transmitting q packets. attnw power state - receiving d packets. av opcode field in row packets. bank a block of 2 rbit ?2 cbit storage cells in the core of the rdram. bc bank address field in colc packet. bbit cnfga register field - # bank address bits. broadcast an operation executed by all rdrams. br bank address field in row packets. bubble idle cycle(s) on rdram pins needed because of a resource constraint. byt cnfgb register field - 8/9 bits per byte. bx bank address field in colx packet. c column address field in colc packet. cal calibrate (i ol ) command in xop field. cbit cnfgb register field - # column address bits. cca control register - current control a. ccb control register - current control b. cfm,cfmn clock pins for receiving packets. channel row/col/dq pins and external wires. clrr clear reset command from sop field. cmd cmos pin for initialization/power control. cnfga control register with configuration fields. cnfgb control register with configuration fields. col pins for column-access control. col colc,colm,colx packet on col pins. colc column operation packet on col pins. colm write mask packet on col pins. column rows in a bank or activated row in sense amps have 2 cbit dualocts column storage. command a decoded bit-combination from a field. colx extended operation packet on col pins. controller a logic-device which drives the row/col /dq wires for a channel of rdrams. cop column opcode field in colc packet. core the banks and sense amps of an rdram. ctm,ctmn clock pins for transmitting packets. current control periodic operations to update the proper i ol value of rsl output drivers. d write data packet on dq pins. dbl cnfgb register field - doubled-bank. dc device address field in colc packet. device an rdram on a channel. devid control register with device address that is matched against dr, dc, and dx fields. dm device match for row packet decode. doubled-bank rdram with shared sense amp. dq dqa and dqb pins. dqa pins for data byte a. dqb pins for data byte b. dqs napx register field - pdn/nap exit. dr,dr4t,dr4f device address field and packet framing fields in rowa and rowr packets. dualoct 16 bytes - the smallest addressable datum. dx device address field in colx packet. field a collection of bits in a packet. init control register with initialization fields. initialization configuring a channel of rdrams so they are ready to respond to transactions. lsr cnfga register field - low-power self- refresh. m mask opcode field (colm/colx packet). ma field in colm packet for masking byte a. mb field in colm packet for masking byte b. msk mask command in m field. mver control register - manufacturer id. nap power state - needs sck/cmd wakeup. napr nap command in rop field. naprc conditional nap command in rop field. napxa napx register field - nap exit delay a. napxb napx register field - nap exit delay b. nocop no-operation command in cop field. norop no-operation command in rop field.
rev.0.9 / dec.2000 63 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary noxop no-operation command in xop field. nsr init register field- nap self-refresh. packet a collection of bits carried on the channel. pdn power state - needs sck/cmd wakeup. pdnr powerdown command in rop field. pdnxa control register - pdn exit delay a. pdnxb control register - pdn exit delay b. pin efficiency the fraction of non-idle cycles on a pin. pre prec,prer,prex precharge commands. prec precharge command in cop field. precharge prepares sense amp and bank for activate. prer precharge command in rop field. prex precharge command in xop field. psx init register field - pdn/nap exit. psr init register field - pdn self-refresh. pver cnfgb register field - protocol version. q read data packet on dq pins. r row address field of rowa packet. rbit cnfgb register field - # row address bits. rd/rda read (/precharge) command in cop field. read operation of accesssing sense amp data. receive moving information from the channel into the rdram (a serial stream is demuxed). refa refresh-activate command in rop field. refb control register - next bank (self-refresh). refbit cnfga register field - ignore bank bits (for refa and self-refresh). refp refresh-precharge command in rop field. refr control register - next row for refa. refresh periodic operations to restore storage cells. retire the automatic operation that stores write buffer into sense amp after wr command. rlx rlxc,rlxr,rlxx relax commands. rlxc relax command in cop field. rlxr relax command in rop field. rlxx relax command in xop field. rop row-opcode field in rowr packet. row 2 cbit dualocts of cells (bank/sense amp). row pins for row-access control row rowa or rowr packets on row pins. rowa activate packet on row pins. rowr row operation packet on row pins. rq alternate name for row/col pins. rsl rambus signaling levels. sam sample (i ol ) command in xop field. sa serial address packet for control register transactions w/ sa address field. sbc serial broadcast field in srq. sck cmos clock pin.. sd serial data packet for control register transactions w/ sd data field. sdev serial device address in srq packet. sdevid init register field - serial device id. self-refresh refresh mode for pdn and nap. sense amp fast storage that holds copy of bank?s row. setf set fast clock command from sop field. setr set reset command from sop field. sint serial interval packet for control register read/write transactions. sio0,sio1 cmos serial pins for control registers. sop serial opcode field in srq. srd serial read opcode command from sop. srp init register field - serial repeat bit. srq serial request packet for control register read/write transactions. stby power state - ready for row packets. sver control register - stepping version. swr serial write opcode command from sop. tcas tclscas register field - t cas core delay. tcls tclscas register field - t cls core delay. tclscas control register - t cas and t cls delays. tcycle control register - t cycle delay. tdac control register - t dac delay. test77 control register - for test purposes. test78 control register - for test purposes. trdly control register - t rdly delay. transaction row,col,dq packets for memory access. transmit moving information from the rdram onto the channel (parallel word is muxed). wr/wra write (/precharge) command in cop field. write operation of modifying sense amp data. xop extended opcode field in colx packet.
64 rev.0.9/dec.2000 direct rdram ? 256/288-mbit (512kx16/18x32s) preliminary table of contents overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 key timing parameters/part numbers . . . . . . . . . . . 1 pinouts and definitions . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 field encoding summary . . . . . . . . . . . . . . . . . . . . . . 8 dq packet timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 colm packet to d packet mapping . . . . . . . . . . . . 10 row-to-row packet interaction . . . . . . . . . . . . . . 12 row-to-col packet interaction . . . . . . . . . . . . . . . 13 col-to-col packet interaction . . . . . . . . . . . . . . . . 14 col-to-row packet interaction . . . . . . . . . . . . . . . 15 row-to-row examples . . . . . . . . . . . . . . . . . . . . . 16 row and column cycle description . . . . . . . . . . . . 17 precharge mechanisms . . . . . . . . . . . . . . . . . . . . . . 18 read transaction - example . . . . . . . . . . . . . . . . . . 20 write transaction - example . . . . . . . . . . . . . . . . . . 21 write/retire - examples . . . . . . . . . . . . . . . . . . . . . . 22 interleaved write - example . . . . . . . . . . . . . . . . . . . 24 interleaved read - example . . . . . . . . . . . . . . . . . . 24 interleaved rrww . . . . . . . . . . . . . . . . . . . . . . . . . 24 control register transactions . . . . . . . . . . . . . . . . . 26 control register packets . . . . . . . . . . . . . . . . . . . . . 27 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 control register summary . . . . . . . . . . . . . . . . . . . . 30 power state management . . . . . . . . . . . . . . . . . . . . 38 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 current and temperature control . . . . . . . . . . . . . . 44 electrical conditions . . . . . . . . . . . . . . . . . . . . . . . . 46 timing conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 47 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 49 electrical characteristics . . . . . . . . . . . . . . . . . . . . . 50 rsl clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 rsl - receive timing . . . . . . . . . . . . . . . . . . . . . . . 52 rsl - transmit timing . . . . . . . . . . . . . . . . . . . . . . . 53 cmos - receive timing . . . . . . . . . . . . . . . . . . . . . 54 cmos - transmit timing . . . . . . . . . . . . . . . . . . . . . 56 rsl - domain crossing window . . . . . . . . . . . . . . . 57 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 58 absolute maximum ratings . . . . . . . . . . . . . . . . . . . 59 i dd - current profile . . . . . . . . . . . . . . . . . . . . . . . . . 59 capacitance and inductance . . . . . . . . . . . . . . . . . . 60 center-bonded ubga package . . . . . . . . . . . . . . . . 61 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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